06/05/08 Biscotti: a Framework for Token-Flow based Asynchronous Systems Charlie Brej

06/05/08 Overview  The tool problem  Proposed system  Biscotti components  Their current state  Example uses  Conclusions  And future work

06/05/08 The Tool Problem

06/05/08 Wagging Flow Problem TLF Read Async Trans. Desynchronise Netlist Flatten Timing Library Timing Extract Netlist Flatten Verilog Write Simulation Performance Verilog Read Async Trans. Wag

06/05/08 Commercial Tools  Unsuitable  Critical path extraction  Broken  Timing extraction of cyclic designs  Inflexible  Limited simulation trace extraction  Unimplemented  DI logic synthesis

06/05/08 Biscotti Aims  Complete framework for token flow systems  Aims to recreate all tools required to make a design  Modular  Set of libraries  Open Source  GPLv3  Expandable and Customisable  Trivial to add or replace any part with own version

06/05/08 Current Biscotti Components

06/05/088 Parts VerilogTLF VerilogSDF Simulation Netlist Operations TimingWagging Async Transformations Tech-map

06/05/089 Input  Verilog  Modules, Gates  UDPs with MVL extensions  No behavioral  TLF  Cell characterisations  Splines  In: Capacitance and Slew  Out: Delay and Slew primitive trinary_C(Z,A,B); output Z; input A, B; reg Z; table // A B : Z : Z’ 0 0 : ? : 0; 1 1 : ? : 1; 2 2 : ? : 2; ? ? : ? : -; endtable endprimitive

06/05/0810 Output  Verilog  Patchy  Generates verilog executable with NC-Verilog  SDF  Timing extraction files used by external simulators

06/05/0811 Processing 1  Netlist Operations  Internal netlist representation  Allows constructing, altering, flattening...  The basis of all other tools  Timing  Cell timing characteristics (TLF)  Circuit timing extraction  Characterisation of constructed modules

06/05/0812 Processing 2  Pipeline Synthesis  Takes a directed flow graph (DFG) style circuit  Constructs latches and acknowledge trees  Can expand to early output, DIMS or MVL  Creates RAM wrappers and wagging fork/join blocks

06/05/08 C Pipeline Synthesis Logic Async Logic Async Latch Async Latch Async Latch Async Latch Async Latch

06/05/0814 Processing 2  Pipeline Synthesis  Takes a directed flow graph (DFG) style circuit  Constructs latches and acknowledge trees  Can expand to early output, DIMS or MVL  Creates RAM wrappers and wagging fork/join blocks

06/05/0815 Processing 3  Wagging  Duplicates circuit and reconnects latches to form a ring  Inserts abstract fork/join blocks  Simulation  Fast simulator  Slowest trace extraction  MVL capable  Allows simulation at an abstract level

06/05/0816 Processing 4  Tech mapping  Dumb generation of large primitives (balanced trees)  Table based re-synthesis of C-element blocks  Logic blocks in the future  Slowest trace based gate replacement (drive strength)

06/05/08 Example Uses

06/05/0818 Timing extraction Verilog Read TLF Read Netlist Flatten Timing Extract Verilog Write SDF Write

06/05/0819 Extract Slowest Path Verilog Read TLF Read Netlist Flatten Timing Extract Simulation Slowest Trace Slowest Path Write

06/05/0820 Drive Strength Optimisation Verilog Read TLF Read Netlist Flatten Timing Extract Simulation Slowest Trace Tech-map Find Better Cell Netlist Replace Element Verilog Write

06/05/08 Large C-element generation Verilog Read TLF Read Async Trans C-element Gen Timing Extract Tech-map Find Better Cell Verilog Write Timing Generate Splines TLF Write

06/05/08 Conclusions

06/05/08 Current state  Pre-alpha  Pretty unusable  Used to generate RedStar  Parts implemented when needed  About 6 months from public beta  Currently available on request

06/05/08 Future Work  Implement RedStar using system  Using as few commercial tools as possible  Example design  Complete system back-end components  Implement front-end  Scripting of operations  GUI  Benchmark suite

06/05/08 Biscotti Conclusions  Allows implementation of asynchronous designs  Without relying on commercial tools  Tools suited to asynchronous designs  Easy expansion  Allows rapid evaluation of researched techniques  Fairly compare to existing methods  Useful analysis techniques  Still incomplete

06/05/08 Thank you