4/28/05Ray: ELEC7250 1 Fault Diagnosis Using Fault Dictionaries and Probability Adam Ray April 28, 2005.

Slides:



Advertisements
Similar presentations
CSCI 660 EEGN-CSCI 660 Introduction to VLSI Design Lecture 7 Khurram Kazi.
Advertisements

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.
Selection Control Structures Chapter 5: Selection Asserting Java © Rick Mercer.
An Algorithm for Diagnostic Fault Simulation Yu Zhang Vishwani D. Agrawal Auburn University, Auburn, Alabama USA 13/29/2010IEEE LATW 10.
Static Single Assignment CS 540. Spring Efficient Representations for Reachability Efficiency is measured in terms of the size of the representation.
BASIC BUILDING BLOCKS -Harit Desai. Byzantine Generals Problem If a computer fails, –it behaves in a well defined manner A component always shows a zero.
10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.
Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.
VIII - Working with Sequential Logic © Copyright 2004, Gaetano Borriello and Randy H. Katz 1 Finite state machine optimization State minimization  fewer.
1 Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan Vishwani D. Agrawal Department of Electrical and Computer.
Compaction of Diagnostic Test Set for a Full-Response Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal 18th IEEE North Atlantic Test Workshop, 2009.
4/20/2006 ELEC7250 Project: Grimes 1 Logic Simulator for Hierarchical Bench Hillary Grimes III – Term Project ELEC 7250 – Spring 2006.
Parallel Pattern Single Fault Propagation for Combinational Circuits VLSI Testing (ELEC 7250) Submitted by Blessil George, Jyothi Chimakurthy and Malinky.
4/27/2006 ELEC7250: White 1 ELEC7250 VLSI Testing: Final Project Andrew White.
4/28/05 Raghuraman: ELEC To Generate a Single Test Vector to detect all/most number of faults in a given set Project by: Arvind Raghuraman Course.
4/25/2006 ELEC7250: Hill 1 Brad Hill ELEC 7250 Logic Simulator.
4/20/2006ELEC7250: Alexander 1 LOGIC SIMULATION AND FAULT DIAGNOSIS BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION.
A Two Phase Approach for Minimal Diagnostic Test Set Generation Mohammed Ashfaq Shukoor Vishwani D. Agrawal 14th IEEE European Test Symposium Seville,
ELEC 7250 Term Project Presentation Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL.
Spring 07, Feb 8 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence Vishwani D. Agrawal James J.
Spring 08, Mar 27 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Fault Simulation Vishwani D. Agrawal James J.
ELEC7250: VLSI Testing Spring 2004 Experimental Analysis of Fault Collapsing Methods Dixit, Ayoush M.
Exclusive Test and its Application to Fault Diagnosis Vishwani D. Agrawal Dong Hyun Baik Yong C. Kim Kewal K. Saluja Kewal K. Saluja.
04/25/2006 ELEC 7250 Final Project: Jie Qin 1 Logic Simulator for Combinational Circuit Jie Qin Dept. of Electrical and Computer Engineering Auburn University,
Dominance Fault Collapsing of Combinational Circuits By Kalpesh Shetye & Kapil Gore ELEC 7250, Spring 2004.
Jan. 11, '02Kim, et al., VLSI Design'021 Mutiple Faults: Modeling, Simulation and Test Yong C. Kim University of Wisconsin, Dept. of ECE, Madison, WI 53706,
4/26/05Cheng: ELEC72501 A New Method for Diagnosing Multiple Stuck- at-Faults using Multiple and Single Fault Simulations An-jen Cheng ECE Dept. Auburn.
Class Design Project - Test Generation 1 Class Design Project Test Generation Hillary Grimes III ELEC Project Presentation April 26, 2007.
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits Raja K. K. R. Sandireddy and Vishwani D. Agrawal Dept. Of Electrical and Computer.
Algebraic Properties.
CSCI 347 / CS 4206: Data Mining Module 04: Algorithms Topic 06: Regression.
Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault.
Verifying Trigonometric Identities Dr. Shildneck Spring, 2015.
SENG521 (Fall SENG 521 Software Reliability & Testing Fault Tolerant Software Systems: Techniques (Part 4b) Department of Electrical.
$1,000,000 $500,000 $100,000 $50,000 $10,000 $5000 $1000 $500 $200 $100 Is this your Final Answer? YesNo Question 2? Correct Answer Wrong Answer.
CS430 © 2006 Ray S. Babcock LZW Coding Lempel-Ziv-Welch.
Dominance Fault Collapsing 1 VLSI TESTING PROJECT Dominance Fault Collapsing Anandshankar Mudlapur Arun Balaji Kannan Muthu Balaji Ramkumar Muthu Balan.
CAS 721 Course Project Minimum Weighted Clique Cover of Test Set By Wei He ( )
A four function ALU A 00 ADD B MUX SUB 11 Result AND OR
ALGORITHMS.
Abdul-Rahman Elshafei – ID  Introduction  SLAT & iSTAT  Multiplet Scoring  Matching Passing Tests  Matching Complex Failures  Multiplet.
Introduction to Fault Tolerance By Sahithi Podila.
Adiabatic Quantum Computing Josh Ball with advisor Professor Harsh Mathur Problems which are classically difficult to solve may be solved much more quickly.
1 Introduction to Turing Machines
1 Computing Functions with Turing Machines. 2 A function Domain Result Region has:
Speaker: Nansen Huang VLSI Design and Test Seminar (ELEC ) March 9, 2016 Simulation-Based Equivalence Checking.
Multiplication Timed Tests.
PROBABILITY AND COMPUTING RANDOMIZED ALGORITHMS AND PROBABILISTIC ANALYSIS CHAPTER 1 IWAMA and ITO Lab. M1 Sakaidani Hikaru 1.
Distributive Property of Multiplication 306 x 2
Lesson 4 - Challenges.
Dominance Fault Collapsing
VLSI Testing Lecture 14: System Diagnosis
Lecture 7: Repeating a Known Number of Times
Handouts Software Testing and Quality Assurance Theory and Practice Chapter 6 Domain Testing
VLSI Testing Lecture 6: Fault Simulation
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
VLSI Testing Lecture 6: Fault Simulation
Defect and High Level Fault Modeling in Digital Systems
Multiplying 3 digits by 2 digits
Overview: Fault Diagnosis
MSIS 655 Advanced Business Applications Programming
Automatic Test Generation for Combinational Circuits
Testing for Faults, Looking for Defects
Computing Functions with Turing Machines
Garimella Srinivas Gottiparthy Ramraj Vippa Prakash
Veeraraghavan Ramamurthy
Sungho Kang Yonsei University
Unit 8 Tracing Algorithms.
Theory: Question B & C For this task it has ask me to construct the ML(Maximum Likelihood) Table. Finally, I need to find the probability that the ML(Maximum.
Presentation transcript:

4/28/05Ray: ELEC Fault Diagnosis Using Fault Dictionaries and Probability Adam Ray April 28, 2005

4/28/05Ray: ELEC Problem Statement Identify which fault occurred in a failing circuit Need a way to quantify inherent uncertainties – Equivalent faults – Truncated test sets Assumptions – Single stuck-at faults – Stuck-at fault is lowest replaceable unit (LRU)

4/28/05Ray: ELEC The Likelihood Function Likelihood of fault i, time t Faults 0,…,m failed at time t-1 N(t)=total # of remaining faults Test1Test2Test3Test4Test5Test6 Fault Fault Fault Fault Fault Fault Fault Likelihood

4/28/05Ray: ELEC Diagnostic Algorithm START LOOP END Assign beginning likelihoods to each fault Apply next test vector to faulty circuit If outputs are faulty (i.e. Test yields “1”) Assign zero likelihood to faults that show “0” for current test vector Else Assign zero likelihood to faults that show “1” for current test vector Redistribute likelihoods using Likelihood Function Repeat LOOP Output final fault likelihoods BeginTest 1Test2Finish Fault1 (0 1 0) Fault2 (1 0 0) Fault3 (1 0 0) Fault4 (0 1 0) Fault5 (0 0 0) Fault6 (0 0 1) Fault7 (0 0 0)

4/28/05Ray: ELEC Results on 4-Bit ALU After Tests 1 & 2 After Tests 5 & 6 After All Tests

4/28/05Ray: ELEC More Results Fault found with several wrong faults

4/28/05Ray: ELEC Add beginning likelihoods Faults (EQUIV)Beginning LikelihoodsEnding Likelihoods ALL OTHER FAULTS{0.003, 0.006, 0.012}0

4/28/05Ray: ELEC Conclusions Algorithm correctly identifies the fault – Equivalent faults are incorrectly identified Likelihood makes results more conclusive Algorithm can be halted at any point New Algorithm for multiple faults