EET 1131 Unit 7 Arithmetic Operations and Circuits Read Kleitz, Chapter 7, skipping Sections 7-4, 7-5, and 7-8. Homework #7 and Lab #7 due next week. Quiz next week. -Handouts: Practice timing diagrams for 74283 and 74181; logical ops slide 17; practice sheet for signed integers. -Take Quiz #6 -We’re taking sections in Chap 7 out of order. Book starts with more theoretical mat’l and moves to more practical mat’l. We’ll reverse that order.

The rules for binary addition are 0 + 0 = 0 Sum = 0, carry out = 0 When a carry in = 1 due to a previous result, the rules are 1 + 0 + 0 = 01 Sum = 1, carry out = 0 -Recall learning addition & subtraction rules as a kid (346+243; 155+197). -Binary is similar, but with far fewer possible combinations of 1-digit numbers. -First, 4 flashcards with no carry; then 4 with carry=0 and 4 with carry=1. 1 + 0 + 1 = 10 Sum = 0, carry out = 1 1 + 1 + 0 = 10 Sum = 0, carry out = 1 1 + 1 + 1 = 11 Sum = 1, carry out = 1

Example Solution Binary Addition Add the binary numbers 00111 and 10101 and show the equivalent decimal addition. Example Solution 1 1 1 00111 7 10101 21 1 1 1 = 28 -Two more examples: 0111+0001; 1001+1011.

Binary Subtraction, Multiplication, Division The textbook also gives rules for doing binary subtraction, multiplication, and division. From a practical standpoint, though, it’s easier to do one of the following: Either convert the numbers from binary to decimal, then perform the arithmetic operation, then convert back to binary. Or use Windows Calculator to perform these operations directly on binary numbers. 4

Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). The inputs and outputs can be summarized on a truth table. The logic symbol and equivalent circuit are: A B S Cout A B S Cout -In logic symbols such as the one shown above, inputs are generally shown on the left (or top) and outputs are shown on the right (or bottom).

Full-Adder By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. A full-adder can be constructed from two half adders as shown: S A B S Cout A A S Sum S A B B Cout S B Cout Cin Cin Cout Symbol for Full Adder

Example Solution Full-Adder B S Cout 1 Sum 1 Example 1 For the given inputs, determine the intermediate and final outputs of the full adder. 1 Cout 1 The first half-adder has inputs of 1 and 0; therefore the Sum =1 and the Carry out = 0. Solution The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the Carry out = 1. The OR gate has inputs of 1 and 0, therefore the final carry out = 1.

Full-Adder Notice that the result from the previous example can be read directly on the truth table for a full adder. A B S Cout 1 Sum This is fine for doing one column in the addition of two multi-bit numbers. For the entire addition, you’ll need as many of these circuits as there are columns in your numbers.

Convention for Writing Multi-Bit Numbers We’ll use subscripts to refer to the individual bits in a binary number. The bit on the right-hand end, or least significant bit (LSB), always gets the smallest subscript, which may be either 1 or 0. Example: In a four-bit number A, the bits are labeled either A4A3A2A1 or A3A2A1A0 -When we have multi-bit numbers, we start numbering (at 0 or 1) from right. Don’t confuse these ID numbers with the column weights. 9

Parallel Adders Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. A B S Cout Cin A1 B1 S1 C0 S2 S3 S4 C1 C2 C3 C4 A2 B2 A3 B3 A4 B4 -Earlier inputs were shown on the left and outputs on the right. Here inputs are shown on the top and outputs on the bottom. -We’re adding two 4-bit numbers. -Example: A=1011, B = 0111.

Parallel Adders The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a Carry In (labeled C0) and a Carry Out (labeled C4). Binary number A Binary number B Carry In 4-bit sum Carry Out 1 2 3 4 C0 C4 S -If you’re just using it to add two 4-bit numbers, you’ll tie C0 to ground. The 74283 is an example.

Two Adder Chips 74283 Four-bit binary adder 7483 is an older chip that is functionally identical to the 74283, but the pins are laid out differently Do practice timing diagram for 74283.

Cascading Parallel Adders When we connect the outputs from one circuit to the inputs of another identical circuit to expand the number of bits being operated on, we say that the circuits are cascaded together. For example, you can cascade two 4-bit parallel adders to add two 8-bit numbers. To do this, connect the lower-order adder’s Carry Out to the higher-order adder’s Carry In. See textbook’s Figure 7-18 (next slide).

Arithmetic Logic Unit (ALU) Central to any computer system is its ALU, which performs mathematical and logical operations on data. In modern systems, the ALU is contained on the computer’s microprocessor chip. In older systems, the ALU was a separate chip, such as the 74181.

How Many Logical Operations? You already know how to perform some logical operations on two input bits, A and B. Examples: X = AB X = A+B Question: How many possible logical operations are there on two input bits?

How Many Logical Ops? (Continued) Let’s list them all: A B 1 Most of these have familiar names; a few do not.

74181 ALU chip Can perform 16 logical operations (bit-by-bit) and 16 arithmetic operations on two 4-bit input numbers. Data Sheet: 74LS181 See next slide (Fig. 7-27 from textbook) for logic symbol and function table.

Figure 7.27 The 74181 ALU: (a) logic symbol; (b) function table. In his function table, I would replace “Mode select” with “Function select.”

74181 ALU (Continued) Caution: In the “Arithmetic Operations” columns of the 74181 function tables, the + symbol always means logical OR, not addition. The word “PLUS” is used for addition.

74181 ALU (Continued) Fourteen Input Pins: A0 to A3 form one of the 4-bit inputs. B0 to B3 form the other 4-bit input. CN is the carry-in bit, used only during arithmetic ops (ignored during logic ops). M is the mode pin (arithmetic or logic). S0 to S3 select the operation performed.

74181 ALU (Continued) Eight Output Pins: F0 to F3 form the 4-bit output. CN+4 is carry-out bit, meaningful only for arithmetic ops. (Ignore it for logic ops.) A=B is comparison bit, meaningful only when performing “A MINUS B” operation. (We’ll ignore this.) P and G are carry-look-ahead bits for high-speed arithmetic, when 74181 is used in conjunction with 74182 chip. (We’ll ignore these.) Do 74181 practice sheet

Terminology: One’s-Complement and Two’s-Complement The one’s-complement of a binary number is the binary number that you get when you invert each bit. Example: What is the one’s-complement of 0011 0101? The two’s-complement of a binary number is the binary number that you get when you invert each bit and then add 1 to the result. Example: What is the two’s-complement of 0011 0101? Do first two questions on practice sheet. 23

Interpreting Strings of 1s and 0s In digital systems we have nothing but 1s and 0s to represent all kinds of info: text, numbers, images, music, etc. To interpret a string of 1s and 0s, you have to be told what kind of info it represents. Example: What does 0100 00012 represent? -Open a text file and a JPG file in Windows Notepad. Possible answers: The number 65. The letter A (in ASCII code). … 24

Unsigned versus Signed Binary Integers Up to now, whenever we’ve worked with binary numbers, we’ve assumed they were unsigned binary integers. In other words, we’ve assumed that the numbers were all positive. Sometimes we also need to be able to represent negative integers, in which case we’re dealing with signed binary integers. To do this, we’ll use one bit to indicate the number’s sign (positive or negative). -So when you interpret a string of 1s and 0s as a number, you’ll also need to know whether it represents an unsigned integer or a signed integer. -Before we see how to do this, let’s review what we know about unsigned integers. 25

Range of Unsigned Binary Integers Arranging unsigned 8-bit integers in order from least to greatest would give you a list that starts and ends like this: Binary Decimal 0000 0000 0 0000 0001 1 0000 0010 2   1111 1101 253 1111 1110 254 1111 1111 255 -Practice sheet: List unsigned 4-bit integers. 26

Range of Unsigned Binary Integers For unsigned integers with a fixed number of bits n: The least integer we can represent is 0. The greatest integer we can represent is 2n-1. Example: Using 8 bits, The least integer is 0000 00002, which is equal to decimal 0. The greatest integer is 1111 11112, which is equal to decimal 255 (=28-1). 27

Representing Signed Binary Integers To represent both positive and negative integers, we use the leftmost bit as a sign bit, like this (for 8 bits): Binary Decimal 1000 0000 -128 1000 0001 -127 1000 0010 -126   1111 1111 -1 0000 0000 0 0000 0001 1   0111 1110 126 0111 1111 127 Negative integers (sign bit = 1) -Practice sheet: List signed 4-bit integers. Zero and positive integers (sign bit = 0) 28

Two’s-Complement Representation The scheme shown on the previous slides is called two’s-complement representation. This is how computers represent signed integers, because this scheme results in simple circuits for doing binary arithmetic. Other common names for it: two’s complement notation or two’s complement form. 29

Range of Signed Binary Integers For signed integers with a fixed number of bits n, the least integer we can represent is −2n−1, and the greatest integer we can represent is 2n−1−1. Example: Using 8 bits, The least integer we can represent is 1000 00002, which is equal to decimal −128 (= −27). The greatest integer we can represent is 0111 11112, which is equal to decimal 127 (= 27-1). 30

Steps for Converting from Decimal to Two’s-Complement Form If the integer is positive, convert it to binary as we’ve always done. If the integer is negative: Ignoring the sign, convert it to binary as we’ve always done. Invert each bit. (That is, change each 0 to 1, and change each 1 to 0.) Add 1 to the result. Examples Convert 2310 to two’s complement form using 8 bits. Convert −2310 to two’s complement form using 8 bits. -This is how our book tells you to do it. There are other ways to do it, which some people find easier to remember. If you’re interested, I can show you. -Do practice sheet questions. 31

Steps for Converting from Two’s-Complement Form to Decimal If the sign bit = 0, the integer is positive. Convert to decimal as we’ve always done. If the sign bit = 1, the integer is negative. Follow these steps: Invert each bit. Add 1. Convert the result to decimal as we’ve always done. Write a negative sign in front. Examples: Convert 0110 0010 to decimal. Convert 1110 0010 to decimal. -This is how our book tells you to do it. There are other ways to do it, which some people find easier to remember. If you’re interested, I can show you. -Do practice sheet questions.. 32

Adding Signed Numbers Using two’s complement form for negative integers simplifies addition and subtraction of signed numbers. Rules for addition: Add the two signed numbers. Discard any final carry out of the MSB. The result is in two’s complement form. Examples: 0001 1110 30 + 0000 1111 + 15 0000 1110 14 +1110 1111 + -17 1111 1111 -1 + 1111 1000 + -8 0010 1101 45 1111 1101 -3 1111 0111 1 -9 Discard carry

Subtracting Signed Numbers Rules for subtraction: Negate the number being subtracted, and then add. Discard any final carry out of the MSB. The result is in two’s complement form. Us the same numbers as on previous slide, but subtract: 0001 1110 0000 1111 - 0000 1110 1110 1111 1111 1111 1111 1000 30 – 15 14 – -17 -1 – -8 Negate the number being subtracted, and then add: 0001 1110 30 +1111 0001 +-15 0000 1110 14 + 0001 0001 +17 1111 1111 -1 + 0000 1000 + 8 0000 1111 1 15 0001 1111 31 0000 0111 1 7 Discard carry Discard carry

An Adder/Subtractor Circuit By combining parallel adder chips (such as the 74283 or the 4008) with a controlled inverter, we can make a circuit that either adds or subtracts, depending on the value of a control input. See next slide (Fig. 7-23 from textbook). 35

Figure 7.23 8-bit two’s-complement adder/subtractor illustrating the subtraction 42 – 23 = 19.