2. Digital Systems
Section 12
Binary Adders

3. Lecture
Digital Systems
Binary Adders
Addition of binary data is very fundamental in digital systems. The hardware implementation needs to be determined.
The inputs are: single bit values, carry in
The outputs are: sum, carry out.
After creating a single-bit adder, we can chain multiple adders together.
Overflow must also be considered. Overflow is the situation where the result of addition exceeds the magnitude which can be represented with the allocated number of bits.

4. Truth Table of Half Adder
Lecture
Digital Systems
Half Adder
A half adder adds two binary numbers.
The inputs: A0, B0 (single bit inputs).
The outputs: S0 (single bit sum) and C1 (carry out).
Truth Table of Half Adder
Circuit of Half Adder
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

5. Lecture
Digital Systems
Multiple Bit Addition
Consider the addition of 2 binary numbers, A and B.
Addition of each bit position Ai and Bi creates a sum Si and a carry Ci+1.

6. Truth Table of Half Adder
Lecture
Digital Systems
Full Adder
A full adder adds two binary numbers but also include a carry in.
The inputs: Ai, Bi, Ci (single bit inputs).
The outputs: Si (single bit sum) and Ci+1 (carry out).
Truth Table of Half Adder
K-Map for Si
K-Map for Ci+1

7. Lecture
Digital Systems
Full Adder
Let us now simplify Boolean function for S by using Boolean algebra.
Si = Ai’Bi’Ci + Ai’BiCi’ + AiBi’Ci’ + AiBiCi
Si = Ci·(Ai’Bi’ + AiBi) + Ci’·(Ai’Bi + AiBi’)
Si = Ci·(Ai  Bi )’ + Ci’·(Ai  Bi )
Si = Ci  (Ai  Bi )
Hint: A  B = A·B’ + A’·B
(A·B)’ = A’ + B’
(A+B)’ = A’ · B’

8. Lecture
Digital Systems
Full Adder
Let us now simplify Boolean function for Ci+1 by using Boolean algebra.
Ci+1 = AiBi + AiCi +BiCi (previous result)
Ci+1 = AiBi + CiAi’Bi +CiAiBi’ (as shown by K-map below)
Ci+1 = AiBi + Ci ·(Ai’Bi + AiBi’)
Ci+1 = AiBi + Ci ·(Ai  Bi)
Hint: A  B = A·B’ + A’·B
(A·B)’ = A’ + B’
(A+B)’ = A’ · B’

9. Full Adder The logic circuit of the full adder can be shown as:
Lecture
Digital Systems
Full Adder
The logic circuit of the full adder can be shown as:
Half adder
Half adder
Si = Ci  (Ai  Bi )
Ci+1 = AiBi + Ci ·(Ai  Bi)
A full adder can be made from 2 half adders and an OR Gate.
Such structure repetition simplifies circuit design.

10. Lecture
Digital Systems
Full Adder =
This single bit full adder will be the building block of large adders.

11. n × Full Adder = n-bit Ripple Carry Adder
Lecture
Digital Systems
n × Full Adder = n-bit Ripple Carry Adder
MSB position
LSB position
4-bit ripple-carry adder

12. Digital Systems
Section 13
Signed Numbers

13. How to Represent Signed Numbers
Lecture
Digital Systems
How to Represent Signed Numbers
For decimal numbers, it is common to use the sign + and –, as for +25, –16, +433, –2775.
For computers, where operations are done using binary digits, it is desirable to represent signed numbers also in bits.
There are 3 representations of signed binary numbers:
Signed magnitude
1’s complement
2’s complement
In each case, the left-most bit indicates the sign: 0 means positive, 1 means negative.

14. How to Represent Signed Numbers
Lecture
Digital Systems
How to Represent Signed Numbers
bn–1
Magnitude
MSB
Unsigned number b1 b0
Magnitude
Sign
0 denotes
1 denotes + –
MSB
Signed number
bn–1 b1 b0
bn–2

15. Lecture
Digital Systems
Signed Numbers
4-bit signed binary number comparison
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 1 + – 2 3 4 5 6 7 8
Number circle for 4-bit 2’s complement numbers

16. 4-bit signed binary number comparison
Lecture
Digital Systems
Signed Numbers
4-bit signed binary number comparison

17. Signed Magnitude Representation
Lecture
Digital Systems
Signed Magnitude Representation
As mentioned before, in signed magnitude, the left-most bit is used to indicate the sign. 0 means positive, 1 means negative.
= 1210
Sign bit
Magnitude
= –1210
Sign bit
Magnitude
By using signed magnitude, n bits can be used to represent integers N in the range of: 2n–1 – 1 ≤ N ≤ 2n–1 – 1
For example, the range of an unsigned 4-bit binary number is from 0 to 15.
The range of a signed 4-bit binary number is –7 to + 7 (or to 01112)
For signed magnitude, there are two representations for zero. For example, with n = 4, 0000 and 1000.

18. 1’s Complement Representation
Lecture
Digital Systems
1’s Complement Representation
The 1’s complement of a binary number involves inverting all bits. 1s become 0s, and 0s become 1s.
As example,
1’s complement of is
1’s complement of is
Thus, for an n-bit number N, the 1’s complement is 2n – 1 – N.
To find the negative of a number, take the 1’s complement of that number.
For 1’s complement, there are two representations for zero. For example, with n = 4, 0000 and 1111.
= 1210
Sign bit
Magnitude
= –1210
Sign bit
Magnitude

19. 1’s Complement Addition / Subtraction
Lecture
Digital Systems
1’s Complement Addition / Subtraction
As Example 1, suppose we wish to add
1210 = = in 1’s complement
110 = = in 1’s complement
Step 1: Add the binary numbers
Step 2: Add the carry to lowest-order bit
011002
000012
011012
011012
= 1310

20. 1’s Complement Addition / Subtraction
Lecture
Digital Systems
1’s Complement Addition / Subtraction
As Example 2, suppose we wish to substract 1210 – 110.
1210 = = in 1’s complement
–110 = –00012 = in 1’s complement
Step 1: Add the binary numbers
Step 2: Add the carry to lowest-order bit
011002
111102 1
010102 1
010112
= 1110

21. 1’s Complement Addition / Subtraction
Lecture
Digital Systems
1’s Complement Addition / Subtraction
As Example 3, suppose we wish to substract –510 – 410.
–510 = –01012 = in 1’s complement
–410 = –01002 = in 1’s complement
Step 1: Add the binary numbers
Step 2: Add the carry to lowest-order bit
110102
110112 1
101012 1
101102
= –10012
= –910

22. 1’s Complement Addition / Subtraction
Lecture
Digital Systems
1’s Complement Addition / Subtraction
As Example 4, suppose we wish to substract –
–510 = –01012 = in 1’s complement
–410 = –01002 = in 1’s complement
Step 1: Add the binary numbers
Step 2: Add the carry to lowest-order bit
110102
001002
111102
111102
= –00012
= –110

23. 2’s Complement Representation
Lecture
Digital Systems
2’s Complement Representation
The 2’s complement of a binary number involves inverting all bits and adding 1.
As example,
2’s complement of is
2’s complement of is
Thus, for an n-bit number N, the 2’s complement is 2n – 1 – N + 1 = 2n – N.
To find the negative of a number, take the 2’s complement of that number.
For 2’s complement more negative numbers than positive.
= 1210
Sign bit
Magnitude
= –1210
Sign bit
Magnitude

24. 2’s Complement Addition / Subtraction
Lecture
Digital Systems
2’s Complement Addition / Subtraction
As Example 5, suppose we wish to add –
–510 = –01012 = in 2’s complement
–910 = –10012 = in 2’s complement
Step 1: Add the binary numbers
Step 2: Discard the carry
110112
010012 1
001002
= 410

25. 2’s Complement Addition / Subtraction
Lecture
Digital Systems
2’s Complement Addition / Subtraction
As Example 6, suppose we wish to add –510 – 910.
–510 = –01012 = in 2’s complement
–910 = –10012 = in 2’s complement
Step 1: Add the binary numbers
Step 2: Discard the carry
110112
101112 1
100102
= –11102
= –1410

26. 2’s Complement Addition / Subtraction
Lecture
Digital Systems
2’s Complement Addition / Subtraction
As Example 7, suppose we wish to substract 1310 – 510.
1310 = –11012 = in 2’s complement
–510 = –01012 = in 2’s complement
Step 1: Add the binary numbers
Step 2: Discard the carry
011012
110112 1
010002
= 810

27. 2’s Complement Addition / Subtraction
Lecture
Digital Systems
2’s Complement Addition / Subtraction
As Example 8, suppose we wish to substract 510 – 1210.
510 = –01012 = in 2’s complement
–1210 = –11002 = in 2’s complement
Step 1: Add the binary numbers
Step 2: Discard the carry
001012
101002
110012
= –01112
= –710

28. Adder-Subtractor Circuit
Lecture
Digital Systems
Adder-Subtractor Circuit
The following circuit is called an adder-subtractor. This circuit is capable of adding and subtracting binary numbers.
When D = 0, the circuit performs addition, S = A + B.
When D = 1, the circuit performs subtraction, S = A – B. The XOR Gates invert the value of B to its 2’s complement (C0 = 1). D

29. Comparing the Signed Numbers
Lecture
Digital Systems
Comparing the Signed Numbers
Signed magnitude:
Negating is very easy  Just change the sign bit
Adding or subtracting is difficult  If the signs are the same, add the magnitudes and keep the sign. If the signs are different, subtract the smaller operand from the larger operand. The sign of the result is the same as the sign of the larger operand.
Rather complex circuit is required.
1’s complement:
Negating is easy  Invert the number but keep the sign bit.
Adding and subtracting is much easier  Include the sign bits, add directly. If there is carry, add it to the sum
Simple but must differentiate cases where carry is 0 or 1.
2’s complement:
Negating is not easy  Invert the number, keep the sign, add 1.
Adding and subtracting is easy  Include the sign bits, add directly. Ignore the carry, directly get the result.
Simple circuit

30. Overflow in Binary Addition and Subtraction
Lecture
Digital Systems
Overflow in Binary Addition and Subtraction
When two numbers of the same sign are added, the answer may not fit the number of bits provided.
In this case, the answer exceeds the magnitude which can be represented with the allotted number of bits. This is called overflow.
In 2’s complement, overflow occurs when a transition is made from 2n–1 –1 to –2n–1 when adding or from –2n–1 to 2n–1 –1.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 1 + – 2 3 4 5 6 7 8

31. Overflow in 4-bit 2 Complement Number
Lecture
Digital Systems
Overflow in 4-bit 2 Complement Number 00
0010
0011
0101 2 3 5 01
0011
0110
1001
Overflow 3 6 –7 11
1110
1101
1011 –2 –3 –5 10
1101
1010
0111
Overflow –3 –6 7 00
0010
1100
1110 2 –4 –2 11
1110
0100
0010 –2 4 2

32. Homework 10 Create a full adder by using NOR Gates only.
Lecture
Digital Systems
Homework 10
Create a full adder by using NOR Gates only.
Convert to decimal from
signed magnitude
1’s complement
2’s complement
Calculate the following equations using signed magnitude:
–810 – 1010 =
2310 – 1710 =
Calculate each of the following equations using 1’s and 2’s complement:
–310 – =
2210 – =
Please write your Class number after your Student ID.
Deadline: 1 day before class.
Monday, 27 November 2017 (Class 2).
Tuesday, 28 November 2017 (Class 1).