FPU structure. Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch –

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Presentation transcript:

FPU structure

Assumptions (to shorten execution trace) – 2 instructions dispatched in order per cycle – execution begins in same cycle as dispatch – result broadcast on CDB in last cycle of execution Example Instruction sequence W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 Initial register contents FLR tagdata F006 F202 F4010 F608

Cycle 1 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit 608 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitW 608 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitW 608

Cycle 2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitW 608 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitW 608 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitW 658

Cycle 3 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitY X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 4 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unitY X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 5 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit X658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 6 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 7 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 8 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit Z658 W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2

Cycle 9 FADDFMUL/DIVFLR tagdatatagdatatagdatatagdatatagdata Ex unit W: F4 <- F0 + F6 X: F2 <- F0 * F4 Y: F4 <- F4 + F6 Z: F6 <- F4 * F2