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Assumptions One instruction can be fetched at each cycle. Latency is 2 cycles for ALU, and 3 for multiplier Instructions begin execution once fetched In.

Published byMelissa Blumer Modified over 9 years ago

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Presentation on theme: "Assumptions One instruction can be fetched at each cycle. Latency is 2 cycles for ALU, and 3 for multiplier Instructions begin execution once fetched In."— Presentation transcript:

1 Assumptions One instruction can be fetched at each cycle. Latency is 2 cycles for ALU, and 3 for multiplier Instructions begin execution once fetched In case two instructions finish at the same cycle, both can commit on the same cycle and the CDB arbitrates who writes first

2 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 6.0 2 3.5 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB

3 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 6.0 2 3.5 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Decode I Cycle 1

4 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 6.0 2 3.5 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Obtain Operands Cycle 1

5 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 6 10 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 6.0 2x 4- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Since writing to R2, R2 data is not valid anymore, obtain new data from RS # 4 Cycle 1 Operands are available, begin execution on next cycle

6 * Op1TagOp2TagRs 10 7.8 1 2 3 RSTagOp1TagOp2 4 6 10 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x1 - 2x 4- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Begin execution BUSY Cycle 1 Since writing to R0, new data is in RS # 1 Cycle 2 Decode J Operands are available, begin execution on next cycle

7 * Op1TagOp2TagRs 10 7.8 1 -1 - 4 2 3 RSTagOp1TagOp2 4 6 10 5 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x1 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB BUSY Cycle 2 K is writing to R2, update the tag to RS#2 BUSY Cycle 1 Cycle 3 Decode K Operands for K not ready, monitor CDB for RS # 1 & 4

8 * Op1TagOp2TagRs 10 7.8 1 -1 - 4 2 3 RSTagOp1TagOp2 4 6 10 5 2 - 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Only one operand is ready. Operand 1 will be fetched from RS # 2 BUSY Cycle 3 BUSY Cycle 2 Cycle 4 Decode L L is writing to R0, update the tag to RS#5

9 * Op1TagOp2TagRs 10 7.8 1 -1 - 4 2 3 RSTagOp1TagOp2 4 6 10 5 2 - 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Done with I, broadcast results on CDB BUSY Cycle 2 Cycle 5

10 * Op1TagOp2TagRs 10 7.8 1 -1 60 - 2 3 RSTagOp1TagOp2 4 5 2 - 10 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Writes results Cycle 5 RS#4 is now free

11 * Op1TagOp2TagRs 1 17.8- 60 - 2 3 RSTagOp1TagOp2 4 5 2 - 10 6 CDB -/+ I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Writes results Cycle 5 RS#1 is now free

12 * Op1TagOp2TagRs 1 17.8- 60 - 2 3 RSTagOp1TagOp2 4 5 2 - 10 6 CDB I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Cycle 6 -/+ BUSY Cycle 1

13 * Op1TagOp2TagRs 1 17.8- 60 - 2 3 RSTagOp1TagOp2 4 5 2 - 10 6 CDB I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder CDB Cycle 7 -/+ BUSY Cycle 2

14 * Op1TagOp2TagRs 1 17.8- 60 - 2 3 RSTagOp1TagOp2 4 5 2 - 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 2x 2- 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Writes results Cycle 8 -/+ CDB

15 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Writes results Cycle 8 -/+ CDB RS#2 is now free Write final results to R2. This is valid data; (most recent), and no other WAW RS 5, observes a write it has been looking for on the CDB (77.8). Now Multiplier can begin execution on cycle 9

16 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Busy, Cycle 1 Cycle 9 -/+ CDB

17 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Busy, Cycle 2 Cycle 10 -/+ CDB

18 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 x5 - 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Busy, Cycle 3 Cycle 11 -/+ CDB

19 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 778 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Writes results Cycle 11 -/+ Write the values to register 0 CDB

20 * Op1TagOp2TagRs 1 2 3 RSTagOp1TagOp2 4 5 77.8 10 6 I: R2 <- R0 * R4 J: R0 <- R4 + R8 K: R2 <- R0 + R2 L: R0 <- R2 * R4 FP.RBusyTagData 0 778 277.8 4 10 8 7.8 Multiplier Reservation Stations ALU Reservation Stations Floating Point Registers Instruction Bank Decoder Writes results -/+ Final floating point register values CDB

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