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CS203 – Advanced Computer Architecture

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1 CS203 – Advanced Computer Architecture
Tomasulo Algorithm - Speculative Superscalar

2 Tomasulo Example Loop: LD R2,0(R1) DADDIU R2,R2,#1 SD R2,0(R1) DADDIU R1,R1,#8 BNE R2,R3,LOOP Assumption: Add/Branch – 1 cycle Load/Store – 1 cycle Addr. Gen 1 cycles Mem. Access *Assume 2-issue superscalar 2 instruction can commit/clock (2 CDB) Memory FP Adder Branch

3 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6
Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) (R2) = 5 DADDIU R2, R2, #1 (R2) = 6 SD R2, 0(R1) Mem[100] = 6 DADDIU R1, R1, #8 (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 2 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 Rob8 Rob7 Rob6 Rob5 Rob4 Rob3 Rob2 Rob1 Tag Op Vj Vk Qj Qk Addr Add1 Add2 Add3 Br1 Br2 Load1 Load2 Load3 Busy field not shown here due to space constraint. If there’s no entry, busy = 0, else busy = 1

4 Cycle 1: LD1 – Issue, ADD1a – Issue
Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) (R2) = 5 DADDIU R2, R2, #1 (R2) = 6 SD R2, 0(R1) Mem[100] = 6 DADDIU R1, R1, #8 (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 2 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 Rob8 Rob7 Rob6 Rob5 Rob4 Rob3 Rob2 ADD R2 Rob1 LD Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 1 Rob1 Add2 Add3 Br1 Br2 Load1 LD 100 Load2 Load3 Cycle 1: LD1 – Issue, ADD1a – Issue

5 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 (R2) = 5 DADDIU R2, R2, #1 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Mem[100] = 6 DADDIU R1, R1, #8 (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 Rob8 Rob7 Rob6 Rob5 Rob4 ADD R1 Rob3 SD 0+(R1) Rob2 R2 Rob1 LD Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 1 Rob1 Add2 Rob4 100 8 Add3 Br1 Br2 Load1 LD Load2 Load3 Cycle 2: LD1 – Calc. Addr., ADD1a – Wait for R2 (LD1), SD1 – Issue, ADD1b - Issue

6 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 (R2) = 5 DADDIU R2, R2, #1 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 Rob8 Rob7 Rob6 Rob5 BNE Rob4 ADD R1 Rob3 SD 100 Rob2 R2 Rob1 LD Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 1 Rob1 Add2 Rob4 100 8 Add3 Br1 Rob5 BNE 10 Br2 Load1 LD Load2 Load3 Cycle 3: LD1 – Load, ADD1a – Wait for R2 (LD1), SD1 – Calc. Addr, ADD1b – Execute, BNE1 - Issue

7 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 (R2) = 5 DADDIU R2, R2, #1 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 Rob8 Rob7 ADD R2 Rob6 LD Rob5 BNE Rob4 R1 108 1 Rob3 SD 100 Rob2 Rob1 5 Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 5 1 Add2 Rob4 100 8 Add3 Rob7 Rob6 Br1 Rob5 BNE 10 Br2 Load1 Rob1 LD Load2 108 Load3 Cycle 4: LD1 – CDB, ADD1a – Wait for R2 (LD1), SD1 – Wait for R2 (ADD1a), ADD1b – CDB, BNE1 – Wait for R2 (ADD1a), LD2 – Issue, ADD2a - Issue

8 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 No Exec. Delay (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 Rob8 SD 0+(R1) Rob7 R2 Rob6 LD Rob5 BNE Rob4 108 1 Rob3 100 Rob2 Rob1 5 Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 5 1 Add2 Rob9 108 8 Add3 Rob7 Rob6 Br1 Rob5 BNE 10 Br2 Load1 Load2 LD Load3 Cycle 5: LD1 – Commit, ADD1a Execute, SD1 – Wait for R2 (ADD1a), ADD1b – Wait to Commit, BNE1 – Wait for R2 (ADD1a), LD2 – Calc Addr., ADD2a – Wait for R2 (LD2), SD2 – Issue, ADD2b - Issue

9 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 No Exec. Delay (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 Rob8 SD 108 Rob7 R2 Rob6 LD Rob5 BNE Rob4 1 Rob3 100 6 Rob2 Rob1 Tag Op Vj Vk Qj Qk Addr Add1 Rob2 ADD 5 1 Add2 Rob9 108 8 Add3 Rob7 Rob6 Br1 Rob5 BNE 6 10 Br2 Rob1 Load1 Load2 LD Load3 Cycle 6: ADD1a CDB, SD1 – Wait for R2 (ADD1a), ADD1b – Wait to Commit, BNE1 – Wait for R2 (ADD1a), LD2 – Load Spec., ADD2a – Wait for R2 (LD2), SD2 – Calc. Addr., ADD2b – Execute, BNE2 - Issue

10 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 7 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 No Exec. Delay (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 116 1 Rob8 SD 108 Rob7 R2 Rob6 LD 6 Rob5 BNE Rob4 Rob3 100 Rob2 Rob1 Tag Op Vj Vk Qj Qk Addr Add1 Add2 Rob9 ADD 108 8 Add3 Rob7 6 1 Br1 Rob5 BNE 10 Br2 Rob1 Load1 Load2 Rob6 LD Load3 Cycle 7: ADD1a – Commit, SD1 – Commit, ADD1b – Wait to Commit, BNE1 – Exec., LD2 – CDB, ADD2a – Wait for R2 (LD2), SD2 – Wait for R2 (ADD2a), ADD2b – CDB, BNE2 – Wait for R2 (ADD2a)

11 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 7 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 No Exec. Delay (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 116 1 Rob8 SD 108 Rob7 R2 Rob6 LD 6 Rob5 BNE Rob4 Rob3 Rob2 Rob1 Tag Op Vj Vk Qj Qk Addr Add1 Add2 Add3 Rob7 ADD 6 1 Br1 Br2 Rob1 BNE 10 Load1 Load2 Load3 Cycle 8: ADD1b –Commit, BNE1 – Commit, LD2 – Wait to Commit, ADD2a – Exec, SD2 – Wait for R2 (ADD2a), ADD2b – Wait to Commit , BNE2 – Wait for R2 (ADD2a)

12 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 7 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 9 No Exec. Delay (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 116 1 Rob8 SD 108 7 Rob7 R2 Rob6 LD 6 Rob5 Rob4 Rob3 Rob2 Rob1 BNE Tag Op Vj Vk Qj Qk Addr Add1 Add2 Add3 Rob7 ADD 6 1 Br1 Br2 Rob1 BNE 7 10 Load1 Load2 Load3 Cycle 9: LD2 – Commit, ADD2a – CDB, SD2 – Wait for R2 (ADD2a), ADD2b – Wait to Commit , BNE2 – Wait for R2 (ADD2a)

13 Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 7 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 9 No Exec. Delay 10 (R2) = 7 Mem[108] = 7 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 116 1 Rob8 SD 108 7 Rob7 R2 Rob6 Rob5 Rob4 Rob3 Rob2 Rob1 BNE Tag Op Vj Vk Qj Qk Addr Add1 Add2 Add3 Br1 Br2 Rob1 BNE 7 10 Load1 Load2 Load3 Cycle 10: ADD2a – Commit, SD2 – Commit, ADD2b – Wait to Commit , BNE2 – Exec

14 Cycle 11: ADD2b – Commit , BNE2 – Commit
Iter Instruction Issue Exec Mem access Wrt. CDB Commit Comment 1 LD R2, 0(R1) 2 3 4 5 (R2) = 5 DADDIU R2, R2, #1 6 7 Wait for R2 (LD) (R2) = 6 SD R2, 0(R1) Wait for R2 (ADD) Mem[100] = 6 DADDIU R1, R1, #8 8 Exec. Directly (R1) = 108 BNE R2, R3, LOOP 6 ≠ 10 9 No Exec. Delay 10 (R2) = 7 Mem[108] = 7 11 (R1) = 116 7 ≠ 10 Assume: (R1) = 100, (R3) = 10, Mem[100] = 5, Mem[108] = 6 Type Dest. Value Ready Rob9 ADD R1 116 1 Rob8 Rob7 Rob6 Rob5 Rob4 Rob3 Rob2 Rob1 BNE Tag Op Vj Vk Qj Qk Addr Add1 Add2 Add3 Br1 Br2 Load1 Load2 Load3 Cycle 11: ADD2b – Commit , BNE2 – Commit

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