Synthesis for Test Virendra Singh Indian Institute of Science Bangalore IEP on Digital System IIT Kanpur

Dec 21, Testability Objective  Improve  Controllability  Observability  Reduction in sequential depth  Elimination of sequential loop

Dec 21, Sequential Depth Reduction - Allocation Allocation Scheme  Enhance controllability and observability  Reduction in Sequential depth Based on RT Architecture Independent of Test Technology

Dec 21, Controllability and Observability a b c d e f g h Lifetime table Allocation 1 R1: a, c, g R2: b, d, h R3: e R4: f

Dec 21, Controllability and Observability a b c d e f g h Lifetime table Allocation 2 R1: a, c, R2: b, d R3: e, f R4: f, g

Dec 21, Controllability and Observability If any one of variable assigned to a register is a PI (PO) of the chip, this register is directly controlled (observed); if not, register can be accessed through other registers Goal: To ensure that as many registers as possible in the implementation are assigned at least PI/PO Each row of register must cover a PI/PO TSR1: Whenever possible, allocate a register to at least one PI or PO

Dec 21, Sequential Depth Reduction SDFG a 2 bde c f g a b c d e f g Lifetime Table

Dec 21, Sequential Depth Reduction TSR1 does not provide inform testability suggestions on module allocation and interconnect allocation Register allocation using TSR1 R = { (a,c,g), (b,f), (d), (e)} Two possible Module allocation M1 ={(+ 1,3 ), (+ 2 )} M2 ={(+ 1,2 ), (+ 3 )}

Dec 21, Sequential Depth Reduction M1 is preferred to save interconnect cost output of +2 is hard to observe An error effect needs to propagate through an additional register R2 before it can be observed

Dec 21, Sequential Depth Reduction R1R2 R4 R3 ab d e g R = { (a,f,g), (b,c), (d), (e)} TSR2: Reduce the sequential depth from an input register to an output register

Dec 21, Sequential Depth Reduction R1R2 R4 R3 ab d e g R = { (a,c,g), (b,f), (d), (e)}

Dec 21, Sequential Loop Reduction SDFG R1(d) 4 R3(c) R2(b) R1(a) R1 R3 R2 Sequential Loop: Reuse of R1

Dec 21, Sequential Loop Reduction x1 x2 a 6 x9 TIME 1 TIME 2 TIME 3 TIME 4 +5 y e b f g c d TIME 5

Dec 21, Sequential Loop Reduction Alloc scheme Register AllocationModule allocation #Mux#loopFC A1R1 =(x1,a), R2=(x4,e,b) R3= (x6,f,c), R4=(x7,d,g) R5= (x9,y) (+1,4) (+2,3) (+3,7) (+5,8) A2R1 =(x6,e,b,c,d,y), R2=(x1,a) R3= (x4,f), R4=(x7,g) R5= (x9) (+1,2) (+6) (+3,7) (+4,5,8)

Dec 21, Sequential Loop Reduction R1 R2 R5 R3 R4 A1

Dec 21, Sequential Loop Reduction R1 R2 R5 R3 R4 A2

Dec 21, Scheduling for Sequential Depth/Loop Reduction TSR3: Reduce Sequential loop by Proper resource sharing to avoid creating sequential loops for cyclic DFG Assign IO registers to break sequential loop TSR4: Schedule operations to support the application of TSR1, TSR2, and TSR3

Dec 21, Controllability + *- a R (b) Primary input R(c) +* - R(a) R(b) Primary input R(c) R = (b,c, …) Not directly controllable R = (a,b,c, …) Directly controllable

Dec 21, Observability R 2 (z) R1 = (….,w,x, …) Not directly observable + * - t t+1 t+2 * R 1 (w) R 2 (y) R 1 (x) t+3 + * - t t+1 t+2 * R 1 (w) R 1 (y) R 1 (x) t+3 R 1 (z)

Dec 21, Sequential Depth Reduction R 2 (z) *1 *2 - t t+1 t+2 + R 1 (w) R 2 (y) R 1 (x) t+3 R 2 (v) R 3 (s) R 3 (u) R 2 (z) *1 *2 - t t+1 t+2 + R 1 (w) R 2 (y) R 1 (x) t+3 R 2 (v) R 3 (s) R 3 (u)

Dec 21, Mobility Path * * * + * * * +< TIME 1 TIME 2 TIME 3 TIME 4

Dec 21, Mobility Path * * * TIME 1 TIME 2 TIME 3 TIME 4

Dec 21, Mobility Path Scheduling Mobility_path_scheduling(G){ 1.ASAP_scheduling(G); 2.ALAP_scheduling(G); 3.Update_op_slack_and_mobility(G); 4.While (unscheduled_op(G) ≠ 0){ 5. P k = next_min_mobility_path(G); 6. partial scheduling(P k, G); 7. testMP(P k, G); / analyze testability on P k 8.} 9.}

Dec 21, Mobility Path Scheduling partial_scheduling(P k,G){ 1.For each (operation o on Pk) 2. if (o.earliest = o.latest) // mobility becomes 0 3. o.active = o.earliest // assign schedule 4.Update_op_slack_and)mobility(G); 5.While (unscheduled_op (P k ) ≠ 0){ 6. (o, o.ll_cycles) = next_op_with _least_no_light_load_cycles(Pk, G); 7. o.active = most_preferred_cycle(o.ll_cycles, G);