1. A Flow Graph Technique for DFT Controller Modification
Mohammad Hosseinabady,
Pejman Lotfi-Kamran,
Pedram Riahi*,
Fabrizio Lombardi*,
Zainalabedin Navabi
Electrical and Computer Engineering, University of Tehran, Iran
*ECE Department, Northeastern University, USA

2. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

3. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

4. Motivation and Objectives
Test generation at the gate-level
produces high-quality tests
But in the case of large systems
It is computationally expensive
Objectives
We propose a DFT algorithm to
Reducing test generation time
Reducing test application time

5. Our Contributions
Realize and utilize existing path of the datapath by changing controller
Previous work
Increase the testability of an RTL module
Use datapath as search space to find test paths
But, we
Increase testability; decrease test application time.
Use the CDFG as search space to find test paths

6. Advantages of Our Algorithm
Reduce test application time
Using pre-computed test vector
Reducing test generation effort
Very small area overhead on controller
No timing penalty of critical path (in the datapath)

7. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

8. CDFG and Synthesis CDFG can be used for extracting control
The behavioral description of a circuit is usually provided using a hardware description language like VHDL. This description is compiled into a control/data flow graph (CDFG), which is a directed graph with operation vertices, data variable arcs, conditions, and loops.
CDFG can be used for extracting control
and data information during synthesis steps
Scheduling
Binding
CLK1 *1 *1 +2 *3 z2 z1 z3
CLK2 *4 +5 3 z4 z6 *6 *7
CLK3 5 z7
CLK4 z5 *8 z8
CLK5 -9 y

9. Datapath & Controller - + * z1,z4,z6,y z3,z7,z8 z2,z5 m1 m2 m3 m4 L1b c d f g 1 2 m5 m6 m7 L3 e 3 5
Group 1
Group 3
Group 2
Group 4 R1 R2 R3

10. Test-Path in the Datapath
Module Under Test
(Pre-computed test vectors are available) g a f 5 c e d b 3 * * + -
Group 2
Group 3
Group 1
Group 4
z3, z7, z8
z2, z5
z1, z4, z6, y

11. A Problem!!! This Test-Path is not supported by the controller!!!
Using the CDFG as the search space,
a controller supported Test-Path can be found

12. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

13. Test-Path in CDFG
The role of a controller is to map the CDFG of a circuit to its datapath. Consequently,
All paths in a CDFG exist in the datapath of a circuit.
However, there may be additional paths in a datapath that do not necessarily exist in a CDFG that the datapath is generated from.

14. Test-Path in CDFG
controller-supported paths: paths in a datapath can be activated for passing data by the existing controller of the circuit.
controller-unsupported paths : paths of the datapath that are not specified by the CDFG and are not activated by the existing controller
To recognize and thus utilize these paths,
changes may be needed in the circuit’s controller.

15. Faulty Operator in the CDFG
If a module in the RTL is faulty, all operators in its group of the CDFG became faulty. This means that multiple faults appear in the CDFG. To avoid this scenario, only one operator is considered as a victim operator as faulty and the CDFG is pruned by deleting all other operators in the group as well as all their connecting nodes.

16. Victim A victim is an existing/new operator that
Receives its inputs from outside of its group and
Propagates its output to outside of its group, and
Pruned CDFG corresponding to the victim operator must have at least a primary output of the original CDFG.

17. Victims Victim Victim a b Victim b a a a a b b b Group i c Group i

18. Test Time Reduction
Test application time can be reduced using two techniques
Finding best victim when a victim has alternatives
Removing unnecessary states in the Pruned CDFG (Explained in the example)

19. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

20. Group 1 * * + - g a f 5 c e d b 3 Group 1 Group 2 Group 3 Group 4
z3, z7, z8
z2, z5
z1, z4, z6, y

21. z1 and y are mapped in the same register in the Datapath
Group 1 Victim e g a b c d f
Victim
CLK1 *1 *1 +2 *3 z2 z1 z3
z1 and y are mapped in the same register in the Datapath
CLK2 *4 +5 3
Group 1 z4 z6 *6 *7
CLK3 5 z7
CLK4 z5 *8 z8
CLK5 -9 y

22. Group1 Testing Pruned CDFG Just one clock cycle is enougha b
Just one clock cycle is enough
to apply each pre-computed
test vector to this RTL module
CLK1 *1 *1 y
Pruned CDFG

23. Group2 * * + - g a f 5 c e d b 3 Group 1 Group 2 Group 3 Group 4
z3, z7, z8
z2, z5
z1, z4, z6, y

24. Group 2 Victim Victim e g a b c d f *1 +2 *3 Group 2 *v z2 z1 z3
z1 and z6 are mapped in the same register in the Datapath *4 +5 3 z4 z5 *6 *7 5 z7 z6 *8 z8 -9
z3 and z8 are mapped in the same register in the Datapath y S1 S2 S3 S4 S5

25. Group 2 Testing a b g f
Just two clock cycles are enough to apply each pre-computed
test vector to this RTL module
CLK1 *1 *3
CLK5 -9 y S1 S2 S3 S4 S5

26. Group4 * * + - g a f 5 c e d b 3 Group 1 Group 2 Group 3 Group 4
z3, z7, z8
z2, z5
z1, z4, z6, y

27. Group4 Victim Group 4 has only one member,
so it is a compulsory victim operator.
The DFG for this victim is the same as the original CDFG .
This CDFG can be reduced by the
elimination of clocks 2, 3 and 4. e g a b c d f
CLK1 *1 *1 +2 *3 z2 z1 z3
CLK2 *4 +5 3 z4 z5 *6 *7
CLK3 5 z7
CLK4 z6 *8 z8
CLK5 -9
Group 4
Victim y

28. Reducing the CDFG Graph of Group 4b c d f
The utilization of shared registers of
the datapath are the basic principle for
reducing the test application time.
Using a bipartite graph the
obtained CDFG is reduced *1 *1 +2 *3 z2 z1 z3 *4 +5 3 z4 z5 *6 *7 5 z7 z6 *8 z8 -9 y

29. Group 4 Testing a b g f
Just two clock cycles are enough to apply each pre-computed
test vector to this RTL module
CLK1 *1 *3
CLK5 -9 y S1 S2 S3 S4 S5

30. Agenda Motivation, Objectives and Contributions
Preliminaries and Our Idea
CDFG Testability and Victim
An Example
Experimental Results

31. Experimental Results

32. Questions!