Georgia Tech Digital Back-end µHRG interface Curtis Mayberry School of Electrical and Computer Engineering Georgia Institute of Technology January 13 th, 2014 Contact:

Topics System Design Digital Processing ADC DAC Power Supply AFE Interface Feed Through Cancellation Tuning Review Measures 2 Topics

System Overview Analog Front End (Red Board) –Device Pad –Pickoff Channels (Node and Antinode) –Forcer Channels (node and Antinode) –Feed-through Cancellation (x4) –Quadrature Amplifiers (50v) Digital Back End (GT BE) –24 bit ADC (8 Channels) and LPF ADC Drivers –16 bit DAC (8 Channels) and Reconstruction LPF –Feed Through Cancellation Tuning Digital Potentiometers Digital Signal Processor (TI Tiva C Launchpad) –80 MHz MCU Development Board 3 System Design

System Diagram 4 System Design

Microcontroller: TI Tiva C Series 80 MHz 32bit MCU (internal PLL to adjust) 4xSPI Serial communication Single Precision Floating point 128 kB Flash Up to 43 GPIOs Tiva C Launchpad –Microcontroller Part Number: TM4C123GH6PMI –On-board ICDI USB programmer and debugger –40 Pin Header to connect to back-end –On-board RGB LED and 2 Switches –USB Powered Digital Processing

Alternative Signal Processor: FPGA Spartan 6 XC6SLX9 FPGA 84 digital IO pins 8 analog inputs 8 general purpose LEDs 1 reset button 1 LED to show when the FPGA is correctly configured On board voltage regulation that can handle 4.8V - 12V A microcontroller (ATmega16U4) used for configuring the FPGA, USB communications, and reading the analog pins On board flash memory to store the FPGA configuration file 6 Digital Processing

Board designed to mate on top of Tiva C series Launchpad Uses female 0.1” Low profile Headers by Samtec to mate with the Launchpad Can use ribbon cable and header strip to reposition Launchpad Connection: Launchpad Interface

Connection: Launchpad Ports Interface

Launchpad Interface Pinout 9 Interface

ADC: High Resolution TI ADS bit, up to 111 dB SNR (52kSPS) 8 Channel, simultaneous sample Up to 144 kSPS (w/ 106 SNR) SPI or Frame-Sync Serial Interface No registers: all settings set by pins (GPIO) Power Supplies –Analog VDD: 5v –Digital Core: 1.8v –IO VDD: 3.3v Initialization –Settings set digitally by GPIOs –Jumpers: Clock input selection and power down selection ADC

ADC Sampling Frequency and Resolution 11 ADC

ADC Schematic: Main 12 Common Mode Buffer Fully Differential ADC Drivers (4ch) Single Ended ADC Drivers (4ch) Clock Input Selection Jumper ADC Shutdown Jumpers ADC

Fully Differential ADC Driver OPA1632 Fully differential Audio Op-amp sets common mode for ADC input LOW NOISE: 1.3nV/√Hz Gain Bandwidth: 180MHz Jumper Option: ground Vin- for single-ended to differential conversion ADC input channels 1-4 –Ch.1: Node Pickoff –Ch. 2: Antinode Pickoff –Ch. 3: Ain 3 –Ch.4: RTD Supply: ±8v Symmetric and Balanced Layout ADC Schematic Layout

AC Simulation Results 14 AC fmax = 10 kHz Gain = 1 (-6 dB for each differential output) Phase = o Corner Frequency: kHz Gain Peaking: 1.07 dB ADC

Transient Simulation Results 15 Input Outputs ADC

ADC Common Mode Voltage Buffer Buffers 2.5v Common Mode Voltage from ADC Op-amp –OPA350 –Low Noise: 5nV/√Hz –Unity-gain stable –Single Supply: 5v ADC Schematic Layout

Voltage Reference ADR v Output Noise (0.1Hz to 10 Hz): <1μVpp Initial Output Voltage Error: 0.02% Input Voltage Range: 3v-15v –(Running off of regulated 5v Rail) Output current:±10mA TCV OUT : 2ppm/ o c Solder Heat Shift: ±0.02% Long Term Drift: o c ADC Reference Schematic Reference Layout Trace to ADC Length: mm Width: 0.35/0.254mm

ADC Layout 18 ADS1278 ADC Fully Differential ADC Drivers (4ch) Single-Ended ADC Drivers Channels 5-8 CH1 Fully Diff ADC Driver CH2 Fully Diff ADC Driver CH3 Fully Diff ADC Driver CH4 Fully Diff ADC Driver Channel Shutdown Jumpers CLK Selection Jumper ADC

DAC: High Resolution ADI AD bit 4 Channel Serial clock: up to 30 MHz Programmable Bipolar/unipolar output – +5 V, +10 V, V, ±5 V, ±10 V, ±10.8 V ( only 5v, ±5 V w/ Vs= ±8 V) INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum Integrated output and reference buffers DAC

DAC Reconstruction Filter 20 2 nd Order Sallen-Key Filter: Fc = 15kHz 1 st Order RC: Fc = kHz Amplitude and Phase: 10kHz: -92o 160kHz: -258o Op-amp Selection OPA 4140: 4 channels/package Noise: 5.1 nV/  Hz Input Bias Current: 0.5pA Id: 2.0 mA Vdd max: ± 18 V SOIC-14 DAC

DAC Reconstruction Filter: AC Simulation Results 21 DAC

DAC Resolution, sampling rate, and DR 22 DAC

DAC Main Schematic 23 DAC: AD5754 Daisychained Reconstruction Filters Output Format Jumper Quadrature Grounding Options DAC

DAC Layout 24 DAC: AD5754 Daisychained Reconstruction Filters Output Format Jumper Quadrature Grounding Options DAC

Connection: External and AFE (“Red” Daughterboard) Interface SMA connectors for power and data connections Only 7 connectors total (3 SMA Supplies + 4 USB) Interface

Digital Potentiometers: Feed-through Cancellation Tuning Digital Potentiometers used to control feedthrough cancellation gains 4 channels total 10kΩ maximum resistance per channel Parallel and series resistors allow adjustment of resistance Interface: 1 SPI channel, 2 CS Screw terminals to connect to AFE 26 Feed Through Cancellation Tuning

Power Supplies: 1.8v, 3.3v, and 5v Regulated 1.8v, 3.3v, and 5v supplies TPS767D318 –Dual Supply: 3.3v and 1.8v LDO –Output Current: 1.0A per regulator –2% Tolerance –Power –on reset unused – maybe I should add this to the reset sources? –Need 3.3v for digital logic –Need 1.8v for ADC core TPS78650 –5.0v LDO –2% Tolerance –Vin: up to 10v (8v used) 27 Power Supply

Layout and Schematic Checks Schematic –ERC: Electrical Rules Check: No Major Problems Layout –DRC: Design Rules Check No Errors –LVS: Layout vs. Schematic: No differences 28 Review

DFM Review 29 Review

Complete Main Schematic 30 Review

3D Visualization 31 Top Bottom Missing 3D Models: 90 degree SMA Connectors, jumper headers Review