Syllabus Instructor: Dr. Wesam Ashour Teaching Assistants: Eng. Eng. Ahmed Eldaly. Eng. Amal El-khalily.    Office: B223 Email: Washour@iugaza.edu Office Hours: Saturday, Monday 10:00  12:00. Sunday, Tuesday 11:00  12:00.

Syllabus Course: ECOM 3310 – Computer Architecture Contents: 1- Ch.1: Introduction. 2- Ch.2: Instructions: Language of the Computer. 3- Ch.3: Arithmetic for Computers. 4- Ch.4: Assessing and Understanding Performance. 5- Ch.5: The Processor: Datapath and Control. 6- Ch.6: Enhancing Performance with Pipelining. 7- Ch.7: Large and Fast: Exploiting Memory Hierarchy 8- Ch.8: Input/Output Systems We will cover as much as we can!

Syllabus Description: Goals of the Course: This course explores the design of computer systems and their architectures. Topics include central processing unit architecture, pipelining, system interconnections, memory systems, input/output systems, interrupt handling.   Goals of the Course: Basic understanding of computer organization: roles of processors, main memory, and input/output devices. Understanding the concept of programs as sequences of machine instructions. Understanding the relationship between assembly language and machine language; development of skill in assembly language programming; understanding the relationship between high-level compiled languages and assembly language. Understanding arithmetic and logical operations with integer operands. Understanding floating-point number systems and operations. Understanding simple data path and control designs for processors. Understanding memory organization, including cache structures and virtual memory schemes. The course include basic machine architecture and design, digital logic circuits, digital components, central processing unit, machine representation of instructions and data, addressing techniques, memory organization, and execution of instructions at machine level.

Syllabus Course Outcomes: By the end of this course, students should be able to: Write a simple program in assembler language to implement a high level program segment Design simple assembly language programs that make appropriate use of a registers and memory. Understand how the architecture affects program performance Understand the basics of computer hardware and how software interacts with computer hardware. Understanding how to implement the instruction set architecture ISA Understanding the levels and organizations of Hierarchies in Memories and cashes. Assemble a simple computer with hardware design including data format, instruction format, instruction set, addressing modes, bus structure, input/output, memory, Arithmetic/Logic unit, control unit, and data, instruction and address flow.

Syllabus Course web site: http://site.iugaza.edu.ps/washour/courses/computer-architecture/ Course Grading: 20% Quizzes + HWs + Teaching Assistant control. 10% Project. 20% Midterm Exam. 50% Final Exam. Midterm Exam: Tuesday, 25th November 2014, 11:00am-12:30pm Final Exam: Monday, 19th January 2015, 11:30am-14:30pm Important Notice: Sometimes (& Suddenly) I will test you by giving Quizzes at the beginning of the lecture! - To solve it easily and to get the highest mark, you should always read the last two lectures before attending the class – Good Luck. Important Advice: From first day in the semester you should work very hard and you must activate your mind to think!

Chapter 2

lw $t0, 1200($t1) add $t0, $s2, $t0 sw $t0, 1200($t1) What is the MIPS machine language code for these three instructions? 1200 (in base 10) = 0000 0100 1011 0000 (binary) $t0 register is number 8 $t1 register is number 9 $s2 register is number 18 Opcode -> lw is 35 (100011), sw is 43 (101011), R-type (000000) add func is 32 (100000)

lw $t0, 1200($t1) add $t0, $s2, $t0 sw $t0, 1200($t1) What is the MIPS machine language code for these three instructions? 1200 (in base 10) = 0000 0100 1011 0000 (binary) $t0 register is number 8 $t1 register is number 9 $s2 register is number 18 Opcode -> lw is 35 (100011), sw is 43 (101011), R-type (000000) add func is 32 (100000) 100011 01001 01000 0000010010110000 000000 10010 01000 01000 00000 100000 101011 01001 01000 0000010010110000

or $t0, $t1, $t2 ori $t0, $t1, 255 sll $t0, $t1, 4 and $t0, $t1, $t2

if (save[i] >= k) Code; Assume save[i] is stored in $t1 and k is stored in $t2

if (save[i] >= k) Code; Assume save[i] is stored in $t1 and k is stored in $t2 slt $t0, $t1, $t2 bne $t0, $zero, Exit Code Exit:

if (save[i] < k) Code; Assume save[i] is stored in $t1 and k is stored in $t2

if (save[i] < k) Code; Assume save[i] is stored in $t1 and k is stored in $t2 slt $t0, $t1, $t2 beq $t0, $zero, Exit Code Exit:

if (save[i] > k) Code; Assume save[i] is stored in $t1 and k is stored in $t2

if (save[i] > k) Code; Assume save[i] is stored in $t1 and k is stored in $t2 slt $t0, $t1, $t2 bne $t0, $zero, Exit beq $t1, $t2, Exit Code Exit:

Try it by yourself if (save[i] <= k) Code; Assume save[i] is stored in $t1 and k is stored in $t2 Try it by yourself