Modulo-N Counters Module M10.4 Section 7.2.

Slides:

Advertisements

Similar presentations

Shift-Registers and Push Button Debounce

Advertisements

Encoders Module M9.3 Section 6.3. Encoders Priority Encoders TTL Encoders.

Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN

Shift Registers Module M11.1 Section 7.3.

7-Segment Displays Lecture L6.1 Section 6.3. Turning on an LED.

//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.

How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.

Binary Counters Module M10.3 Section 7.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

7-Segment Displays Lecture L6.7 Section 6.5. Turning on an LED.

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp

Counter Circuits and VHDL State Machines

Using State Machines as Control Circuits Lecture L9.4.

Multiplier Lecture L7.3 Section 10.4 (p.276) Section 7.3 (Handout)

Pulse-Width Modulated DAC

Multiplexers Lecture L6.4 Section 6.4.

Subtractors Module M8.2 Section 6.2. Subtractors Half Subtractor Full Subtractor Adder/Subtractor - 1 Adder/Subtractor - 2.

Designing State Machines Lecture L9.2 Handout Section 9.2.

Datapaths Lecture L10.2 Sections 10.2, ALU (Sect. 7.5 and Lab 6)

Arbitrary Waveforms Lecture L8.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

Counters as State Machines Lecture L9.1 Handout Section 9.1.

Designing State Machines SQRT controller Lecture L9.2a Section 9.2.

Homework Reading Machine Projects Labs Tokheim Chapter 9.1 – 9.6

Flip-Flops Module M10.2 Section 7.1. D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.

Counters Mano & Kime Sections 5-4, 5-5. Counters Ripple Counter Synchronous Binary Counters –Design with D Flip-Flops –Design with J-K Flip-Flops Counters.

Binary Counters Lecture L8.3 Section 8.2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter.

Shifter Lecture L7.4 Group HW #4 Section 10.3.

Modulo-N Counters Lecture L8.4 Section 7.2. Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter.

Codes and Code Converters

Code Converters Module M7.1 Section 6.5. Code Converters Binary-to-BCD Converters ABEL TRUTH_TABLE Command.

Arbitrary Waveforms Module M10.5 Section 7.2. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s s s s3 0 1.

© Bob York Gates +5 V 1 kΩ Out +5 V A B Out In 1 kΩ +5 V A B Out

Arithmetic Logic Unit (ALU) Lecture L7.5 Section 7.5.

Pulse-Width Modulated DAC Lecture 11.3 Section 11.5.

Multiplexers Module M6.1 Section 6.4. Multiplexers A 4-to-1 MUX TTL Multiplexer A 2-to-1 MUX.

2’s Complement 4-Bit Saturator

Adders Lecture L7.1 Section 6.2 Section 10.4 (pp )

Shifters Lecture L7.4 Section 7.4. MODULE shift TITLE 'shifter' DECLARATIONS " INPUT PINS " D3..D0 PIN 11,7,6,5; D = [D3..D0]; s2..s0 PIN 3,2,1; S.

Flip-Flops Lecture L8.2 Section 8.1. Recall the !S-!R Latch !S !R Q !Q !S !R Q !Q X Y nand 1 0 Set 1 0.

Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Decoders Module M9.1 Section 6.3. Decoders TTL Decoders.

Arithmetic Logic Unit (ALU) Lecture L9.3 Lab 10. ALU CB = carry_borrow flag Z = zero flag (Z = 1 if Y = 0)

CS 140 Lecture 18 Professor CK Cheng 12/3/02. Standard Sequential Modules 1.Register 2.Shift Register 3.Counter.

Shift Registers Lecture L6.6 Section Bit Shift Register.

WinCupl Module M2.2 Section 4.2. Experiment 2 CUPL Header.

7-Segment Displays Module M7.2 Section 6.5. Turning on an LED Common Anode.

Equality Detector Module M5.1 Section 6.1. Equality Detector XNOR X Y Z Z = !(X $ Y) X Y Z

Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.

DIGITAL DESIGN WITH VHDL Exercise 1 1Muhammad Amir Yousaf.

Figure 1.1 The Altera UP 3 FPGA Development board

Department of Communication Engineering, NCTU 1 Unit 2 Reviews on Logic Elements.

displayCtrlr Specification

A Greatest Common Divisor (GCD) Processor Lecture L10.3 Sections 10.4, 10.5.

Digital Electronics.

EE121 John Wakerly Lecture #9

SYEN 3330 Digital SystemsJung H. Kim 1 SYEN 3330 Digital Systems Chapter 7 – Part 2.

Lab 2 Basic Gates in a PLD Module M2.3 Section 4.2 Experiment 2 (p. 63)

Lab5-1 張明峰交大資工系 Lab 5: FSM and BCD counters Implement the vending machine of lab 2 A two-digit BCD counter –two BCD counters –can load data in parallel.

Logiske funktioner i Peel. PEEL 18CV8 logic diagram.

1 Homework Reading –Tokheim Chapter 9.1 – 9.6 Machine Projects –Continue on mp3 Labs –Continue in labs with your assigned section.

Magnitude Comparator Module M5.2 Section 6.1.

Praktikum Mikrokontroler

Counters as State Machines

Shift Registers Lecture L8.6 Section 8.3.

4-Bit Counter Spencer Canavan.

ECE 3130 – Digital Electronics and Design

A register design with parallel load input

Digital Logic & Design Dr. Waseem Ikram Lecture No. 36.

Switching Theory and Logic Design Chapter 5:

14 Digital Systems.

Magnitude Comparator Lecture L6.2 Section 6.1.

Presentation transcript:

Modulo-N Counters Module M10.4 Section 7.2

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

Modulo-5 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D CLK D Q !Q Q0 Q0.D Q1 Q2 Q1.D Q2.D

Modulo-5 Counter Q1 Q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 X X X 1 Q2.D Q2.D = Q1 & Q0

Modulo-5 Counter Q1 Q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 X X X 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

Modulo-5 Counter Q1 Q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 0 0 0 s5 1 0 1 X X X s6 1 1 0 X X X s7 1 1 1 X X X State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 X X X 1 Q0.D Q0.D = !Q2 & ! Q0 Note: On reset output pins are all high. Therefore, we need to include a clear input.

mod5cnt.pld

mod5cnt.abl MODULE Mod5Cnt TITLE ‘Modulo-5 Counter, A. Student, 7/20/02' DECLARATIONS “ INPUT PINS “ PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 " OUTPUT PINS " Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8 Q = [Q2..Q0]; " 3-bit output vector [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display

mod5cnt.abl (cont’d) Note !Clear EQUATIONS Q.c = PB; Q0.d = !Clear & !Q2 & !Q0; Q1.d = !Clear & !Q1 & Q0 # !Clear & Q1 & !Q0; Q2.d = !Clear & Q1 & Q0; DP = PB; " decimal point @radix 16; truth_table ( Q -> Segments ) " 7-segment display … Note !Clear

mod5cnt.abl (cont’d) @radix 16; truth_table ( Q -> Segments ) " 7-segment display 0 -> 7E; 1 -> 30; 2 -> 6D; 3 -> 79; 4 -> 33; 5 -> 5B; 6 -> 5F; 7 -> 70;

mod5cnt.abl (cont’d) test_vectors([PB,Clear] -> Q) [.c.,1] -> 0; END

Simulation File, mod5cnt.si CUPL Simulation File

mod5cnt.si CUPL Simulation File Note: first test vector clears output Back to LLL after 5 states

CUPL Simulation Output File

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

3-Bit Down Counter s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D CLK D Q !Q Q0 Q0.D Q1 Q2 Q1.D Q2.D

3-Bit Down Counter Q1 Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0

3-Bit Down Counter Q1 Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0

3-Bit Down Counter Q1 Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1 Q0.D Q0.D = ! Q0

dncnt3ld.abl If load = 1, Load Data to [q0..2] MODULE DnCnt3LD TITLE '3-bit Down Counter with Clear and Load' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 Load PIN 11; " Switch 3 X2..X0 PIN 71,66,70; " Switch 6..8 Data = [X2..X0]; " 3-bit input vector " OUTPUT PINS " LED1..LED2 PIN 44,43 ISTYPE 'com'; " LED 1..2 timeout PIN 41 ISTYPE 'com'; " LED 3 Q2..Q0 PIN 37,36,35 ISTYPE 'reg buffer'; " LED 6..8 Q = [Q2..Q0]; " 3-bit output vector [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display If load = 1, Load Data to [q0..2] timeout = 1 when [q0..2] = [0,0,0]

dncnt3ld.abl (cont’d) EQUATIONS LED1 = Clear; LED2 = Load; Q.c = PB; WHEN Clear THEN Q.d = 0; ELSE { WHEN Load THEN Q.d = Data; Q2.d = !Clear & !Q2 & !Q1 & !Q0 # !Clear & Q2 & Q1 # !Clear & Q2 & Q0; Q1.d = !Clear & !Q1 & !Q0 # !Clear & Q1 & Q0; Q0.d = !Clear & !Q0; } timeout = !Q0 & !Q1 & !Q2; …

Simulation File, dncnt3ld.si CUPL Simulation File

dncnt3ld.si CUPL Simulation File ORDER: clock,%2,clear,load,%3,I2..0,%3,q0,%2,q1,%2,q2,%2,timeout; VECTORS: C10 XXX LLL H /* clear counter */ C00 XXX HHH L C00 XXX LHH L C00 XXX HLH L C00 XXX LLH L C00 XXX HHL L C01 101 HLH L /* load 101 into counter */ C00 XXX HHL L C00 XXX LHL L C00 XXX HLL L C00 XXX LLL H /* timeout */

CUPL Simulation Output File

Counters Modulo-5 Counter 3-Bit Down Counter with Load and Timeout Modulo-N Down Counter

3-Bit Down Counter with Load and Timeout ______________ | dncnt3ld | clock x---|1 20|---x Vcc clear x---|2 19|---x q0 load x---|3 18|---x q1 I0 x---|4 17|---x q2 I1 x---|5 16|---x timeout I2 x---|6 15|---x x---|7 14|---x x---|8 13|---x x---|9 12|---x GND x---|10 11|---x |______________| To make a Modulo-5 counter, connect [I2..0] to 100 and connect timeout to load.

CUPL Simulation Output File