EEL4712 Digital Design (Midterm 1 Review)

VHDL Modeling Styles A dataflow architecture uses only concurrent signal assignments A behavioral architecture uses only process statements A structural architecture uses only component instantiation statements

Sequential Logic Synthesis for Beginners

For Beginners Use processes with very simple structure only to describe - registers - shift registers - counters - state machines. Use examples discussed in class as a template. Create generic entities for registers, shift registers, and counters, and instantiate the corresponding components in a higher level circuit using GENERIC MAP PORT MAP. Supplement sequential components with combinational logic described using concurrent statements.

Sequential Logic Synthesis for Intermediates

For Intermmediates Use Processes with IF and CASE statements only. Do not use LOOPS or VARIABLES. Sensitivity list of the PROCESS should include only signals that can by themsleves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset) Do not use PROCESSes without sensitivity list (they can be synthesizable, but make simulation inefficient)

For Intermmediates (2) Given a single signal, the assignments to this signal should only be made within a single process block in order to avoid possible conflicts in assigning values to this signal. Process 1: PROCESS (a, b) BEGIN y <= a AND b; END PROCESS; Process 2: PROCESS (a, b) y <= a OR b;

Dual-edge triggered register/counter (2) PROCESS (clk) BEGIN IF (clk’EVENT AND clk=‘1’ ) THEN counter <= counter + 1; ELSIF (clk’EVENT AND clk=‘0’ ) THEN END IF; END PROCESS;

Dual-edge triggered register/counter (3) PROCESS (clk) BEGIN IF (clk’EVENT) THEN counter <= counter + 1; END IF; END PROCESS;

Example 1 Identify any error when the following code is synthesized entity test is generic (width : positive := 8); port( clk : in std_logic; rst : in std_logic; in1, in2 : in std_logic_vector(width-1 downto 0); out1, out2 : out std_logic_vector(width-1 downto 0)); end test; architecture BHV of test is begin process(clk, rst) if (rst = '1') then out1 <= (others => '0'); out2 <= (others => '0'); elsif (rising_edge(clk)) then out1 <= in1; end if; end process; out2 <= std_logic_vector(unsigned(in1)+unsigned(in2)); end BHV;

Example 2 entity mult is generic( width : positive := 16); port ( input1, input2 : in std_logic_vector(width-1 downto 0); output : out std_logic_vector(width-1 downto 0); overflow : out std_logic); end mult; architecture BHV4 of mult is begin process(input1, input2) variable temp : unsigned(2*width-1 downto 0); temp := unsigned(input1) * unsigned(input2); output <= std_logic_vector(temp(width-1 downto 0)); if (temp(2*width-1 downto width) /= 0) then overflow <= '1'; end if; end process; end BHV4;

Example 3 The following code is correct and will synthesize to combinational logic, but what suggestion does it not follow? architecture BHV3 of mult is signal temp : unsigned(2*width-1 downto 0) := (others => '0'); begin temp <= unsigned(input1) * unsigned(input2); output <= std_logic_vector(temp(width-1 downto 0)); process(temp) if (temp(2*width-1 downto width) = 0) then overflow <= '0'; else overflow <= '1'; end if; end process; end BHV3; Signals and variables should not be initialized in synthesizable code.

Example 4 Identify any violations of the synthesis coding guidelines for sequential logic process(clk, rst) begin if (rst = '1') then output <= (others => '0'); elsif (rising_edge(clk)) then output <= input; end if; if (en = '1') then output2 <= input; end process; It has been defined outside of If rst Elsif rising_edge(clk) End if

Signals vs Variables If you assign several values to a signal in one process, only the final value is used entity xor_sig is port (A, B, C: in STD_LOGIC; X, Y: out STD_LOGIC); end xor_sig; architecture SIG_ARCH of xor_sig is signal D: STD_LOGIC; begin SIG:process (A,B,C) D <= A; -- ignored !! X <= C xor D; D <= B; -- overrides !! Y <= C xor D; end process; end SIG_ARCH;

Signals vs Variables When you assign a value to a variable, the assignment takes place immediately. A variable maintains its value until you specify a new value. entity xor_var is port (A, B, C: in STD_LOGIC; X, Y: out STD_LOGIC); end xor_var; architecture VAR_ARCH of xor_var is begin VAR:process (A,B,C) variable D: STD_LOGIC; D := A; X <= C xor D; D := B; Y <= C xor D; end process; end VAR_ARCH;

Test bench Given the following entity, specify the widths of each instantiation entity test is generic ( width : positive := 32); port ( in1 : in std_logic_vector(width-1 downto 0); in2 : in std_logic_vector(width-1 downto 0); output : out std_logic_vector(width-1 downto 0)); end test; ----- U_A : entity work.test generic map (width => 16) port map (in1 => in1, in2 => in2, output => output); ---- U_B : entity work.test --- When entity test is used as the top-level entity. 16 32 32

Delays The delay mechanism shows propagation times of described systems. Based on switching time of transistors The information regarding propagation delays are provided in sdo files Delays are specified in signal assignment statements. It is not allowed to specify delays in variable assignments Timing simulations are different than functional simulations

Carry Look Ahead Adders Carry equation: 𝑐 𝑖+1 = 𝒙 𝒊 𝒚 𝒊 + 𝒙 𝒊 + 𝒚 𝒊 𝑐 𝑖 Simplified: 𝑐 𝑖+1 = 𝑔 𝑖 + 𝑝 𝑖 𝑐 𝑖 𝑔 𝑖 = 𝑥 𝑖 𝑦 𝑖 𝑝 𝑖 = 𝑥 𝑖 + 𝑦 𝑖 For example 𝑐 3 = 𝑔 2 + 𝑝 2 𝑐 2 𝑐 3 = 𝑔 2 + 𝑝 2 𝒈 𝟏 + 𝒑 𝟏 𝒈 𝟎 + 𝒑 𝟏 𝒑 𝟎 𝒄 𝟎 𝑐 3 = 𝑔 2 + 𝑝 2 𝑔 1 + 𝑝 2 𝑝 1 𝑔 0 + 𝑝 2 𝑝 1 𝑝 0 𝑐 0

For Generate entity test is architecture STR of test is generic(width : positive := 8); port ( clk, rst, shift, input : in std_logic; output : out std_logic); end test; architecture STR of test is component ff port ( clk, rst, D : in std_logic; Q : out std_logic); end component; component mux2x1 in1, in2, sel : in std_logic; output : out std_logic); -- signal definations begin U_FF0 : --code should be inserted --code should be inserted U_FFS : U_MUX : -- output should be assigned end STR;

Solution begin architecture STR of test is U_FF0 : ff port map ( clk => clk, rst => rst, d => input, q => q(0) ); U_FFS : for i in 1 to width-1 generate U_FF : ff port map ( d => mux_out(i), q => q(i) U_MUX : mux2x1 port map ( in1 => input, in2 => q(i-1), sel => shift, output => mux_out(i) end generate U_FFS; output <= q(width-1); end STR; architecture STR of test is component ff port ( clk, rst, D : in std_logic; Q : out std_logic); end component; component mux2x1 in1, in2, sel : in std_logic; output : out std_logic); signal q : std_logic_vector(width-1 downto 0); signal mux_out : std_logic_vector(width-1 downto 1);

Example Implement the illustrated circuit in VHDL library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity example is generic ( width : positive := 16); port ( clk,rst : in std_logic; in1, in2, in3, in4 : in std_logic_vector(width-1 downto 0); out1, out2 : out std_logic_vector(width-1 downto 0)); end example;

Solution architecture BHV of example is signal reg_in1, reg_in2, reg_in3, reg_in4 : unsigned(width-1 downto 0); signal sum_no_reg : unsigned(width-1 downto 0); begin process(clk, rst) if (rst = '1') then reg_in1 <= (others => '0'); reg_in2 <= (others => '0'); reg_in3 <= (others => '0'); reg_in4 <= (others => '0'); out1 <= (others => '0'); out2 <= (others => '0'); elsif (clk'event and clk = '1') then reg_in1 <= unsigned(in1); reg_in2 <= unsigned(in2); reg_in3 <= unsigned(in3); reg_in4 <= unsigned(in4); out1 <= std_logic_vector(reg_in1 + reg_in2); out2 <= std_logic_vector(sum_no_reg + reg_in4); end if; end process; sum_no_reg <= reg_in2 + reg_in3; end BHV;

References https://buzztech.in/vhdl-modelling-styles-behavioral-dataflow-structural/

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