Interrupts and Exception Handling Input and Output Programmed IO Interrupts and Exception Handling 0 – Programmed IO 1 – Memory mapped vs isolated 2 - The Exception Mechanism 3 - The Role of the Operating System 4 - The MIPS RISC Exception Mechanism 5 - A Sample Exception Handler 6 - Operating System Issues

MAL Input Example WaitLoop: lw $14, KeyboardStatus andi $14, 0x1 beqz $14, WaitLoop lw $2, KeyboardData Note: KeyboardStatus is 0xffff0000 KeyboadData is 0xffff0004 Bit 0 of KeyboardStatus is the ready bit 1 means ready, 0 means not ready. Hardware changes the ready bit.

MAL Output Example Note DisplayStatus is 0xffff0008 WaitLoop: lw $14, DisplayStatus andi $14, 0x1 beqz $14, WaitLoop sw $2, DisplayData Note DisplayStatus is 0xffff0008 DisplayData is 0xffff000c Bit 0 of DisplayStatus is the ready bit 1 means ready, 0 means not ready. Hardware changes the ready bit.

Programmed I/O The previous examples are known as programmed I/O. This means that I/O is initiated by the CPU which checks status bits periodically. This wastes CPU time while it waits for the device to become ready. (spinwaiting) CPU can miss characters that are typed when the program is doing something else. Two other types of I/O control we will look at are interrupt I/O and DMA (Direct Memory Access).

Kbd Echo Reads the keyboard input register, then echos the input to the display

DMA

Interrupts 2 3 1 4 CPU executes Interrupt Handler Interrupt Handler Some code Jr $27 to return to Main 3 Program Main PC When IRQ arrives, Interrupt Handler called. 1 Add a,b,c Next instruction is executed after return from Handler 4 Sub a,b,c

OS - Kernel Responsible for all processes on the machine Is a protected resource User programs must make requests to Kernel. This includes interrupt and exception handling.

MIPS RISC Exception Mechanism Two modes of operation: User or Kernel. Upper half of memory reserved for OS. 0x8000 0000 .. 0xFFFF FFFF Exception Handler starts at 0x8000 0080 OS 0x80000000 Stack Segment 0x7fffffff Data Segment Test Segment 0x400000 Reserved

MIPS RISC Exception Mechanism Only special procedures are allowed access to kernel User’s are not allowed to modify code in the kernel. Nor, access Interrupt handler. System with lots of power. Kernel memory and User Memory are distinct. Security rights prevent users from accessing kernel memory.

Asynchronous Exceptions (Interrupts) Generated by h/w devices. Interrupts, can appear at any time State of system is not known in advance. We cannot count on any general purpose register being free. 2 registers $k0, $k1 ($26, $27) are kernel reserved to cleanly transition to and from an interrupt. This prevents clobbering information stored in user program registers.

Synchronous Exceptions (Traps) Traps are exceptions generated by software. Thus are Predictable Handed by the OS. Device drivers Buffer flush Service routines VM Page Fault Fatal coding errors Divide by Zero Overflow Memory violation. User program tries to access kernel memory, or another user programs memory.

Processors Main Processor (CPU) Co-processor 1 (FPU) - 32 general registers $0 .. $31 - LO & HI for multiply & divide Co-processor 1 (FPU) Physically there are 32 32-bit registers - 16 floating point registers $f0, $f2, .. $f30 Co-processor 0 - BadVAddr, Cause, Status, Exception Program Counter (EPC) registers

Co_processor 0

Co-processor 0 $8 - Bad Virtual Address $12 - Status Register $13 - Cause Register $14 - Exception Program Counter mfc0 Rdest, C0src move from co-processor 0 mtc0 Rsrc, C0dest move to co-processor 0

Cause Register . . . IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0 31 - 16 15 14 13 12 11 10 9 8 7 6 - 2 1 0

Cause Register Interrupt Pending IP - Interrupt Pending bits Six interrupts in bits 10 .. 15 IP(2) .. IP(7) Two simulated interrupts in bits 9 .. 8, s/w IP(0) .. IP(1) By examining the bits software can determine which device is requesting service. 1 = interrupt has occurred but not yet serviced

Status Register Kernel/User Mode Bit subscript meaning 1 c current 3 p previous 5 o old KU - kernel or user mode. bits 1,3,5 0 = kernel, 1 = user. Kernel must return it to the state it was in before the exception occurred. c p o bits act as a 3 layer h/w stack.

Status Register Interrupt Enable Bit subscript meaning 0 c current 2 p previous 4 o old Interrupt Enable. bits 0,2,4 1 means interrupts are allowed c p o are a simple 3 layer h/w stack to store the state of the Interrupt enable

Status Register Interrupt Mask IM - Interrupt Mask bits - Six interrupts in bits 10 .. 15 OR IM(2) .. IM(7) 2 simulated interrupts in bits 9 .. 8 OR IM(0) .. IM(1) By setting the bits software can specify which devices are enabled/disabled. 1 = interrupts allowed, 0 = interrupts disabled

EPC Register ($14) Holds return address for exception handler Exceptions can come from anywhere user program (syscall) kernel (trap) external (device) When an exception is raised: Must save the return address in EPC Normally return address is done with JAL but it is not used when an exception occurs. An exception can occur between JAL and the saving of $ra. Making the use of $ra problematic.

EPC Register ($14). Example Interrupt is received PC is saved in EPC PC is modified to point to the handler. When done PC is reloaded with EPC.

Interrupt Process Interrupt Occurs Return address is automatically stored in EPC Disable Interrupts (done by OS) Save status of machine (create an AR) Save current state of interrupts and KU mode May enable interrupts at this point Handler address is calculated by indexing the Jump table using ExcCode Execute Handler Return from exception. Enable interrupts Restore registers $k0 is loaded with EPC jr $k0

Returning from the Handler - Register Values are restored. - The value in the EPC, $14 of C0 is loaded into $k0 ($26) - rfe instruction Restore From Exception restores the user mode and interrupt enable bits by "shifting" the 6 ls bits in the status register - jump to the location in register $k0

Re-entrant and Non Re-entrant Handlers Interrupts maybe disabled so an interrupt can not interrupt a handler. These handlers then must execute to completion before another interrupt into the handler is allowed. Non re-entrant. E.g. Kbd handler interrupted by the Kbd is bad. key sequences can then arrive out of order. However, kbd handler can be interrupted by a bad address handler. Safe operation Generally this is done on a case by case basis.

Disabling Interrupts 1 - Set (make it 0) bit zero of the status register to disable all interrupts. 2 - Set an individual bit or bits in the Interrupt Mask to disable one or more.

Priority Interrupts Interrupts have priorities. Lower interrupts, higher priority. Typically the timer has highest. Sends an interrupt at regular intervals so OS always has control. Prevents processes from hogging the CPU. Kbd is 2nd. Always good for the user to have control. Handlers are executed based on priority.

Interrupts on PCs prior to 2000 IRQ 0 - Timer IRQ 8 - Real Time Clock IRQ 1 - Keyboard IRQ 9 - Open (Redirected IRQ 2) IRQ 2 - Cascade IRQ 10 - Open (Triggers IRQs 8 to 15) IRQ 3 - Com 2, Com 4 IRQ 11 - Open IRQ 4 - Com 1, Com 3 IRQ 12 - Open IRQ 5 - Open IRQ 13 - Math Coprocessor (Lpt2:, if present) IRQ 6 - Floppy Disk IRQ 14 - Fixed Disk IRQ 7 - LPT1: IRQ 15 - Open

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