Progress on the 40 MHz SEU Test System based on DE2 Board

Slides:

Advertisements

Similar presentations

Controller Tests Stephen Kaye Controller Test Motivation Testing the controller before the next generation helps to shake out any remaining.

Advertisements

1 Power Management for High- speed Digital Systems Tao Zhao Electrical and Computing Engineering University of Idaho.

Preparation run Tezzaron-Chartered A.Rozanov 1 Introduction Restarts test on PS en Avril 2009 Mesure PS SEU chip SEU-IBM Mhz avec FPGA.

[ 1 ] LVDS links Servizio Elettronico Laboratori Frascati INFN - Laboratori Nazionali di Frascati G. Felici LVDS links.

Max-Planck-Institut für Gravitationsphysik - Albert-Einstein-Institut DC Meeting Golm - Karsten Kötter1 Current status of DAQ System

18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.

RADIO FREQUENCY MODULE. Introduction  An RF module is a small electronic circuit used to transmit and receive radio signals.  As the name suggests,

Stop Watch Sean Hicks Dongpu Jin ELEC 307 Project 2 Instructor: Alvaro Pinto April/12/2011.

1 Simple FPGA David, Ronald and Sudha Advisor: Dave Parent 12/05/2005.

4 currents 3 currents 8 signals Motor Pump Interior Electronics (Proposed) 72 bits Differential/Summing Amps 6 Total 12-bit A/D 6 Total Transmitter 6 signals.

Status of the Optical Multiplexer Board 9U Prototype This poster presents the architecture and the status of the Optical Multiplexer Board (OMB) 9U for.

FPGAs and IRRADIATED FPGAs for the LHCb UPGRADE Bin Gui, Ray Mountain.

4 currents 3 currents 8 signals Motor Pump Interior Electronics (Proposed) 72 bits Differential/Summing Amps 6 Total 12-bit A/D 6 Total Transmitter 6 signals.

Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.

4 Dec 2001First ideas for readout/DAQ1 Paul Dauncey Imperial College Contributions from all of UK: result of brainstorming meeting in Birmingham on 13.

Various Topics Related to FEB Liang Han, Ge Jin University of Science and Technology of China Dec.21,2013.

U niversity of S cience and T echnology of C hina Design for Distributed Scheme of WCDA Readout Electronics CAO Zhe University of Science and Technology.

USB controller chip USB connector Spartan-III FPGA as a main controller D Connector for 5 volt DC voltage in SMA connector for external clock / sync On.

Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control.

1 Warsaw University of Technology Faculty of Electronics and Information Technology Institute of Electronic Systems HARDWARE SIMULATOR of the high-resolution.

7/23 Timers in Coldfire Processor Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang Lee (480)

Communication Systems I. How can information flow from point A to point B?

FSS Review 18th August Opto-isolator:Opto-isolator: Top 4 frequency bits set by DIP switchTop 4 frequency bits set by DIP switch FPGA controls bits.

FPGA IRRADIATION and TESTING PLANS (Update) Ray Mountain, Marina Artuso, Bin Gui Syracuse University OUTLINE: 1.Core 2.Peripheral 3.Testing Procedures.

2004 MAPLD, Paper 190 JJ Wang 1 SEU-Hardened Storage Devices in a 0.15 µm Antifuse FPGA – RTAX-S J. J. Wang 1, B. Cronquist 1, J. McCollum 1, R. Gorgis.

Leo Greiner IPHC meeting HFT PIXEL DAQ Prototype Testing.

September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.

© 2008 RoboRubik1 11 Technical Communication Skills Practicum Theory of Operation and Hardware Design Narrative.

Design studies of a low power serial data link for a possible upgrade of the CMS pixel detector Beat Meier, Paul Scherrer Institut PSI TWEPP 2008.

Why we need adjustable delay? The v1495 mezzanine card (A395A) have a signal transmission time about 6ns. But we need all the signals go into the look.

FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.

Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.

1 DAQ Update MEG Review Meeting, Feb. 17 th 2010.

PROGRESS ON ENERGY SUM ELECTRONIC BOARD. VXS Backplane Energy Sum 18 fADC VME64 High Speed Serial VME64 16 CH Detector Signals Crate Sum to Trigger Energy.

Tests of the Fully Loaded CSC Track Finder Backplane M.Matveev S.-J. Lee Rice University Alex Madorsky University of Florida 2 May 2005.

PS/2 Mouse/Keyboard Port

09/01/2016James Leaver SLINK Current Progress. 09/01/2016James Leaver Hardware Setup Slink Receiver Generic PCI Card Slink Transmitter Transition Card.

1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN.

LHCb Calorimeter Upgrade Meeting – 10th September 2012 – CERN LHCb Calorimeter Upgrade Electronics: ASIC solution status E. Picatoste, D. Gascon Universitat.

09/02/20121 Delay Chip Prototype & SPI interface Joan Mauricio La Salle (URL) 15/02/2013.

Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans.

HCC Derived Clocks. Generated Clocks The HCC generates two clocks from the ePLL 160 MHz clocks and the chip 40 MHz clock, used as a reference: An 80 MHz.

Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – March TOTEM System in H8 - Overview, Block Diagram and Main Characteristics Applications -

J. Ye SMU Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN 1 Test Results on LOC1 and Design considerations for LOC2 LOC1 test results:

July 10, 2001 Status Report of the ROD Testing at BNL Kin Yip Activity update of the ROD system at BNL: DAQ-1 with trigger controller Data corruption testing.

1 Timing of the calorimeter monitoring signals 1.Introduction 2.LED trigger signal timing * propagation delay of the broadcast calibration command * calibration.

October 12th 2005 ICALEPCS 2005D.Charlet The SPECS field bus  Global description  Module description Master Slave Mezzanine  Implementation  Link development.

GPL Board Pattern Generator for the Level-0 Decision Unit Hervé Chanal, Rémi Cornat, Emmanuel Delage, Olivier Deschamps, Julien Laubser, Jacques Lecoq,

Xilinx V4 Single Event Effects (SEE) High-Speed Testing Melanie D. Berg/MEI – Principal Investigator Hak Kim, Mark Friendlich/MEI.

C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.

Report on the progress of the 40MHz SEU Test System based on DE2 Board 20 Jan in CPPM Zhao Lei.

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25.

LHCb Outer Tracker Electronics 40MHz Upgrade

XPC Control Target A/D Converter P10021 LVAD Motor Controller

Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011

Data transmission characterization with underwater copper link

Irradiation test results for SAMPA MPW1 and plans for MPW2 irradiation tests Sohail Musa Mahmood

ECE 353 Introduction to Microprocessor Systems

Overview & status of SEU Test Bench

FPGA IRRADIATION and TESTING PLANS (Update)

R&D activity dedicated to the VFE of the Si-W Ecal

VLVNT08 Toulone April 2008 Low Power Multi-Dynamics Front-End Architecture for the OM of a Neutrino Underwater Telescope Domenico Lo Presti Istituto Nazionale.

EUDET – LPC- Clermont VFE Electronics

Table 1: The specification of the PSICM and the ePSICM Prototypes

Communication Systems.

Lecture 5: Cables types and channels

New DCM, FEMDCM DCM jobs DCM upgrade path

Computer Networks Bhushan Trivedi, Director, MCA Programme, at the GLS Institute of Computer Technology, Ahmadabad.

Interfacing keyboard with FPGA

Red Pitaya with EPICS Andraz Pozar EPICS Collaboration Meeting

Presentation transcript:

Progress on the 40 MHz SEU Test System based on DE2 Board Feb. 01, 2010 In CPPM By Zhao Lei

Test about the crosstalk from clock to psout signals from SEU chip to interface board Waveform of the ‘psout’ signal of Channel 5 Waveform of the ‘psout’ signal of Channel 6

Test about the crosstalk from clock to psout signals from SEU chip to interface board Waveform of the ‘psout’ signal of Channel 6 when 1 wire is used as ground line Waveform of the ‘psout’ signal of Channel 6 when 2 wires are used as ground lines After modification of the transmission of the clock signal

Long Time Test Results --Test Mode 0 : static test without read back

Long Time Test Results --Test Mode 0 (40 MHz , 2 hours)

Long Time Test Results --Test Mode 0 (160 kHz , 24 hours)

Long Time Test Results --Test Mode 1 : static test with read back

Long Time Test Results --Test Mode 1 (40 MHz , 2 hours)

Long Time Test Results --Test Mode 1 (160 kHz , 24 hours)

Long Time Test Results --Test Mode 2 : Test versus frequency based on latches

Long Time Test Results --Test Mode 2 (40 MHz , 2 hours)

Long Time Test Results --Test Mode 3 : Test versus frequency based on DFFs

Long Time Test Results --Test Mode 3 (40 MHz , 2 hours)

Waveform of the psout signals (blue) and error signal (red) in FPGA as for data pattern “11111” in Test mode 3

Waveform of the psout signals (blue) and error signal (red) in FPGA as for data pattern “00000” in Test mode 3

Conclusion The crosstalk from the clock to psout signals could be greatly reduced by better shielding of ground. From the long time test, the FPGA and software is approved to work well and stably in long time. The system could run up to 40 MHz, and no errors occur for the first 3 test modes. Errors occur in test mode 3 with very low Bit Error Rate, which are probably due to ground, power supply or the electronic characteristics of the chips.

Thanks