Research: Past, Present and Future Philip Sweany 10/27/06

Past Retargetable Compilers Register Assignment Instruction Scheduling

Retargetable Compilation Rocket C compiler, written in C++ Retargetable for ILP computers Single machine description file Development 1989-2000 Gnu Scale

Instruction Scheduling Local (Basic Block) Global --- Dominator-Path Scheduling Software Pipelining Heuristic search Genetic algorithms Simulated Annealing Integer-Linear programming

Register Assignment Early vs. Late CRAIG Clustering Our algorithm degrades 10% over ideal Next best degrades 19% over ideal

Paritioned Register Banks F1 F2 F3 F4 F5 F6 F7 F8 Register A Register B

Current --- Compilation Hybrid Architectures Multithreading Memory Optimization Scratch-pad memory Tradeoff cache, scratch-pad Architectural Support Function Reuse Split Cache

Hybrid Computing Tradeoffs of performance, power, flexibility Heterogeneous processors on single chip “CPU” FPGA ASIC N “CPU”s, M FPGAs, K ASICs Tradeoffs of performance, power, flexibility

Generic Hybrid Computer CPU 1 FPGA 1 FPGA 2 CPU 2 Shared Memory CPU m FPGA n Multi-CPU Multi-FPGA

Hy-C System Specification Source Code Partitioning CPU Compiler FPGA Power-Performance Model FPGA Power-Performance Model

Multithreading Identify threads from SSA SDF – Scheduled Dataflow Multithreaded Decouple memory access, execution Clusters for scalability

SDF Clusters SP SP … EP EP EP EP C0 Cn-1

Future Automatic Code Generation (I don’t believe in software) Visual Programming of Components