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2015/6/21\course\cpeg421-2010F\Topic-1.ppt1 CPEG 421/621 - Fall 2010 Topics I Fundamentals.

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Presentation on theme: "2015/6/21\course\cpeg421-2010F\Topic-1.ppt1 CPEG 421/621 - Fall 2010 Topics I Fundamentals."— Presentation transcript:

1 2015/6/21\course\cpeg421-2010F\Topic-1.ppt1 CPEG 421/621 - Fall 2010 Topics I Fundamentals

2 Topic I: Outline Part I: Compiler Fundementals An Overview on Compiler Design Compiler Front-End and IR Middle-End: Analysis and Optimizations Back-End: Code Generation and Optimization 2015/6/21\course\cpeg421-2010F\Topic-1.ppt2

3 2015/6/21\course\cpeg421-2010F\Topic-1.ppt3 1.P rocessor architecture design flow 2.Compiler structure and design flow 3.Code generation design flow Foundations for Compiler Design

4 2015/6/21\course\cpeg421-2010F\Topic-1.ppt4 Why Study Compilers? Influences on programming language design Influences on computer design Compiling techniques are useful for software development ─ Parsing techniques are often used ─ Learn practical data structures and algorithms ─ Basis for many tools such as text formatters, structure editors, silicon compilers, design verification tools,… Writing a compiler requires an understanding of almost all important CS subfields

5 2015/6/21\course\cpeg421-2010F\Topic-1.ppt5 Architecture Models Vector architctures, SIMD Instructional Level Parallelism (ILP) superscalar VLIW Multithreaded Architectures Chip multiprocessing (CMP, multi-core, many-core, etc.) GPGPUs Reconfiguratble Archtitectures What is the impact of these ideas on compilers?

6 2015/6/21\course\cpeg421-2010F\Topic-1.ppt6 Instruction Set Architecture Design (Microarchitecture Design-I) System-Level Design RTL Level Design (Microarchitecture Design II) Compiler Design Code Optimizer Hardware Design Switch Level Design Circuit Level design ISA Simulator System Level Simulator RTL Level Simulator Switch Level Simulator Circuit Level Simulator Arch./Compiler and System Software Design Toolset Processor Architecture Design Flow Diagram HDL (VHDL or Verilog) Code Generator Toolchain - Intel VTune™ - IBM Performance Evaluator Debugger

7 2015/6/21\course\cpeg421-2010F\Topic-1.ppt7 Interprocedural Analysis and Optimization Loop Nest Optimization and Parallelization Global (Scalar) Optimization Backend Code Generation Front end Good IR A Good Compiler Infrastructure Needed – A modern View Middle-End

8 2015/6/21\course\cpeg421-2010F\Topic-1.ppt8 Middle-End Optimization Flow Analysis Control flow analysis Dataflow analysis Global scalar optimization Loop nest optimization Advanced topics: Static Single Assignment form (SSA) Application of SSA to scalar optimization

9 2015/6/21\course\cpeg421-2010F\Topic-1.ppt9 Backend Optimization (I) Instruction selection Instruction scheduling Register allocation Others

10 2015/6/21\course\cpeg421-2010F\Topic-1.ppt10 Backend Optimization (II) Loop optimization and scheduling Software pipelining


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