1. CAPS project-team
Compilation et Architectures pour Processeurs Superscalaires et Spécialisés

2. History of CAPS project-team
Project-team created in 1994:
“Compiler Parallel Architectures and Systems”
Common focus:
high performance through optimizing the memory hierarchy
Comes from supercomputer architecture group:
Involved in Marie mini-supercomputer design
late participation in ACRI

3. CAPS: Compiler and Architecture for Superscalar and Special purpose processors
Two interacting activities
microprocessor architecture (A. Seznec, P. Michaud)
High performance
Migrating high performance concepts to embedded systems
Performance oriented compilation (F. Bodin)
Embedded processors
+ Recently: Worst case execution time analysis (I. Puaut)

4. CAPS « missions » Defining the tradeoffs between:
what should be done through hardware
what can be done by the compiler
for maximum performance
or for minimum cost
or for minimum size, power ..

5. Issues on high performance processor architecture
Memory hierarchy management:
1 cycle L1 – 10 cycles L2 – 30 cycles L3 – 200 cycles memory
Branch prediction :
30 cycles penalty x N instructions per cycle
Single cycle next instruction block address generation ?
Complexity quadratic with issue width:
Register file, bypass network, issue logic
Single chip hardware thread parallelism is available:
How do we exploit it ?
Power/temperature

6. Issues on code generation/software environments for embedded processors
ILP, caches are entering embedded processor world
Code generation must manage them
Binary compatibility is not critical, time-to-market is critical
Retargetable platforms are wanted:
ISAs, architecture
Performance is not the only ultimate goal:
Code size/ performance
Power/ performance
System cost/ performance

7. Recent scientific contributions (1) Processor architecture
Global history branch predictors and instruction fetch front-end
2bcgskew used in Compaq EV8
Pipelining the I-fetch front end
Limiting hardware complexity on superscalar processors
Dataflow prescheduling: instruction window
WSRS architecture: register file, bypass network and issue logic
Thread parallelism and single chip parallelism:
CASH: CMP and SMT hybrid
Execution migration: single thread on a multicore, to use all the cache space

8. Recent scientific contributions (2) architecture/compiler interaction
ISA simulation:
ABSCISS: ISA and architecture retargetable high speed simulator for VLIW processor
IATO: simulation of out-of-order execution IA64
Low power and architecture configurability:
Cache reconfiguration at software level on phase basis
Hardware/software speculative management of data path and register file width
SWARP: retargetable C-to-C preprocessor to enhance multimedia instruction use

9. Recent scientific contributions (3) compiler and software environments
Artificial intelligence in performance tuning
CAHT: case based reasoning for assisting performance tuning
Automatic derivation of compiler heuristics: using machine learning to derive compiler heuristics
Performance code size tradeoffs:
Iterative compilation
Mixing interpretation on compressed code and native execution

10. “New-CAPS” objectives (1)
High-end microprocessor architecture:
From “ultimate performance” to “ maintaining performance to cheaper”
Migrating “high-end” concepts to embedded processors:
(limited) O-O-O execution
Compiler/architecture power management

11. “New-CAPS” research objectives (2)
Embedded systems are more and more complex:
performance often comes with unpredictability and unstabibility
Dimensioning a system ?
Real time constraints ?
Research on performance predictability and stability:
Predictable/stable performance oriented code generation
Predictable/stable performance oriented architecture

12. “New-CAPS” research objectives (3)
On-chip thread parallelism is a new opportunity:
Homogeneous: SMT/CMP
Tradeoffs, sharing, synchronization
Heterogeneous:
single ISA
Power, performance,
multiple ISAs (e.g. SoC)
Thread extraction

13. What can we bring in SCIPARC at architecture level ?

14. CAPS pipeline background
« ancient » background in hardware management of ILP: both research and implementation
decoupled pipeline architectures:
Involved in the design of Marie mini-supercomputer 86-88
OPAC, an hardware matrix floating-point coprocessor
1991: 300 ICs, a VLSI sequencer, ..

15. CAPS background in microarchitecture
Solid knowledge in microprocessor architecture
technological watch on microprocessors
+ research on processor architecture
+ A. Seznec worked at Alpha Development Group in :
Defined the EV8 branch predictor
+ P. Michaud worked at Intel ( )

16. Background in memory hierarchy
Interleaved memories for vector supercomputers (research):
+ A. Seznec participated at Tarantula project: vector extension to Compaq EV8
International CAPS visibility in cache architecture :
skewed associative cache
+ decoupled sectored cache

17. Our expertise may help to define next machine in SCIPARC
Bring pipeline definition expertise
Bring memory hierarchy definition expertise
Help to remain simple
Help to enlarge possible application domains