HardWireTM FpgASIC The Superior ASIC Solution CORES Xilinx is the only PLD company capable of combining dense FPGA’s with pre-verified LogiCores that can be converted to Xilinx fpgASIC products for volume cost reductions. This gives the ASIC and the FPGA customer solutions for total product life cycle support. 1

Agenda Conversion Experience Success Stories Conversion Process Conversion Time

Xilinx Has Seven Years of FPGA Conversion Experience Over 800 Xilinx FPGA’s Converted Over 5 Million Devices Shipped >95% first-time-right Prototypes Experience with Complex Designs PCI High RAM Usage Asynchronous Clocks Only Xilinx has experience since 1991 converting only Xilinx designs. This means we are most familiar with our own technology, and we build our HardWire ASIC technology to specifically match the features and functionality of our FPGA’s. We ship high volume as well. We support HardWire devices into key volume markets such as PC, cellular phones, GPS and printer peripherals. Xilinx has vast experience converting many complex features from FPGA to ASIC. PCI, Dual Port RAM and configuration logic can be tricky unless converted by a party who knows the technology. Xilinx knows its own features. 1

HardWire Success Application: Arcade Video Game FPGA: XC4020E-2PQ208 Features: Dual port RAM, PCI Logicore (Initiator and Target) Comment: Attempted to do standard ASIC with several manufacturers with no success. Solution: Only the HardWire ASIC solution was able to incorporate the logic and features providing a cost effective solution. HardWire Device: XC4420-PQ208C Projected Volume: 120-200KU per year. 1

HardWire Success Application: Controller chip in three chip telecom chipset. FPGA: XC4020E-3PQ208I Features: Dual port RAM, JTAG and Configuration Emulation. Comment: Needed fast time to market cost effective solution. Internal solution could not meet time to market requirements. Solution: HardWire ASIC provided production quality samples 7 weeks after the design submittal kit was received. Including package change. HardWire Device: XC4420-TQ100C Projected Volume: 100-300KU per year. Sold to several phone companies 2

HardWire Success Application: six chip encryption chipset for next generation phone/radio base station. FPGA: XC3030-5PC84I, XC5204-4PQ100, XC4005E-3PQ100. Features: SelectRAM, JTAG and Configuration Emulation. Comment: Limited engineering resources available to complete conversion process. Time to completion critical for end customer. Solution: Used different HardWire technologies to match features and performance with most cost effective solution. Production quality samples delivered 6 weeks after complete design submittal kit received. HardWire Device: XC3330-PC84I, XC5404-PQ100I, XC4405-PQ100C Projected Volume: 10-20KU per year. 3

Ensure Conversion Success Use good ASIC design practices Fully synchronous design methodology Acceptable timing margins in chip periphery Position GND pins to avoid problems with simultaneous switching outputs Fully test designs in the FPGA Run Design Rule Check - make sure there are no errors Communicate Requirements as Soon as Possible RAM/JTAG/Configuration Emulation I/O drives and slew rate Any special timing issues Submit Clear, Accurate, Complete Documentation Following these simple points can lead to a better first time success rate. 2

HardWire Conversion Flow Customer XILINX Design Submittal: Form Design file Schematic Design Check DesignLockTM Conversion Timing Analysis TBLK Insertion Design Sign-off Build Prototype: Vector Generation Mask Generation Fab, Assembly, Test The conversion flow from Xilinx FPGAs to HardWire Arrays is simple and straight forward. The customer submits the .LCA file developed for the FPGA, and a schematic. Xilinx factory applications staff will run a Design Review. After the design review is signed by the customer, Xilinx generates prototypes on a production line, and ships the prototypes to the customer for testing. Once the customer verifies the HardWire prototype devices work the same as the FPGA, the Prototype Approval form is signed and Xilinx can produce volume quantity units. Evaluate & Approve Proto HardWire Production 1

HardWire DESIGNLOCK Conversion Reduces Re-design Risk FPGA HardWire Relative placement and routing is preserved throughout the flow. This is true for all generations of HardWire technology. The benefit to the customer is that the risk of design malfunction due to timing errors is virtually eliminated. All CLBs and nets are preserved - No netlist transformation Unused CLB/logic is not mapped for optimal die size CLBs & nets are maintained in the same relative location on the die.

HardWire CLB Based Mapping Preserves Functionality CLB Mapping Preserves Placement ASIC Place and Route is Random By Design Because we focus on mapping a design at the CLB level, rather than the gate level, placement is preserved when moving from the FPGA to the ASIC. The ASIC device is exactly as small as it can possibly be, because the programmable elements are pulled out and because today’s technologies are pad limited.

DesignLocktm Methodology Minimizes Change HardWire ASIC DesignLocktm Methodology: Placement, Routing and Relative Timing Preserved FPGA DEVICE ROUTING Generic ASIC Routing Can Change Critical Paths Through the DesignLock process, the routing is preserved as much as possible in the HardWire device as well. All constraints and relationships in the FPGA design files are carried over to the ASIC. The less disruption to the device through conversion means the less need for re-verification and full simulations of the translated design.

Complete Submittals Speed Conversion Completed Design Submittal Form Disk containing all files: .LCA, .MBO,.BIT, .XRP files for XACT (.NCD, .BIT, .BITSTREAM files for M1) A board- level schematic showing FPGA pinouts NRE purchase order 3

HardWire Conversion Time is a Function of FPGA Density 1997 1998 Average design density 5 – 20KG 50 – 100KG Total conversion time 2-4 weeks 5 – 10 weeks Average gates per week 2-5KG 10 – 15KG 1

Set Expectations Early Conversion Time Set Expectations Early * Add queue time, add customer sign-off/evaluation time. 2