4-Input Gates VHDL for Loops

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Presentation transcript:

4-Input Gates VHDL for Loops Discussion D1.3 Example 3

4-Input AND Gate Behavior: zv := '1'; for i in 1 to 4 loop 3-Level Behavior: zv := '1'; for i in 1 to 4 loop zv := zv and x(i); end loop; 2-Level

-- Example 3: 4-input AND gate - VHDL for loop library IEEE; use IEEE.STD_LOGIC_1164.all; entity and4 is port( x : in STD_LOGIC_VECTOR(4 downto 1); z : out STD_LOGIC ); end and4; architecture and4 of and4 is begin and4_1: process(x) variable zv: STD_LOGIC; zv := x(1); for i in 2 to 4 loop zv := zv and x(i); end loop; z <= zv; end process and4_1;

architecture and4 of and4 is begin and4_1: process(x) variable zv: STD_LOGIC; zv := x(1); for i in 2 to 4 loop zv := zv and x(i); end loop; z <= zv; end process and4_1; end and4; process sensitivity list Sequential statements (for…end loop) must be in a process Note begin…end in process

variables declared before begin architecture and4 of and4 is begin and4_1: process(x) variable zv: STD_LOGIC; zv := x(1); for i in 2 to 4 loop zv := zv and x(i); end loop; z <= zv; end process and4_1; end and4; variable assignment operator := executed immediately signal assignment operator <= updated at end of process

Aldec Active-HDL Simulation

4-Input OR Gate Behavior: zv := '0'; for i in 1 to 4 loop 3-Level Behavior: zv := '0'; for i in 1 to 4 loop zv := zv or x(i); end loop; 2-Level

4-Input XOR Gate Behavior: zv := '0'; for i in 1 to 4 loop 3-Level Behavior: zv := '0'; for i in 1 to 4 loop zv := zv xor x(i); end loop; 2-Level Note: zv = 1 if the number of 1 inputs in ODD