Semiconductor Device Modeling & Characterization Lecture 20 Professor Ronald L. Carter ronc@uta.edu Spring 2001 L20March 29

Equivalent circuit above OSI Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 Depl cap, C’d,min = eSi/xd,max Oxide cap, C’Ox = eOx/xOx Net C is the series comb C’Ox C’d,min L20March 29

MOS surface states** p- substr = n-channel L20March 29

n-substr accumulation (p-channel) Fig 10.7a* L20March 29

n-substrate depletion (p-channel) Fig 10.7b* L20March 29

n-substrate inversion (p-channel) Fig 10.7* L20March 29

Ideal 2-terminal MOS capacitor/diode conducting gate, area = LW Vgate=VG -xox SiO2 y L silicon substrate tsub Vsub=VB x L20March 29

Band models (approx. scale) metal silicon dioxide p-type s/c Eo Eo Eo qcox ~ 0.95 eV qcSi= 4.0eV qfm= 4.28 eV for Al Ec qfs,p Eg,ox ~ 8 eV EFm Ec EFp EFi Ev Ev L20March 29

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev L20March 29

Values for gate work function, fm L20March 29

Values for fms with metal gate L20March 29

Values for fms with silicon gate L20March 29

Experimental values for fms Fig 10.15* L20March 29

Calculation of the threshold cond, VT L20March 29

Equations for VT calculation L20March 29

Fully biased n-MOS capacitor VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y L20March 29 L

Effect of contacts, VS and VD L20March 29

Computing the D.R. width at O.S.I. Ex Emax x L20March 29

Computing the threshold voltage L20March 29

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Fully biased MOS capacitor in inversion VG>VT Channel VS=VC VD=VC EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y L20March 29 L

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev L20March 29

Flat-band parameters for n-channel (p-subst) L20March 29

MOS energy bands at Si surface for n-channel Fig 8.10** L20March 29

Fully biased n- channel VT calc L20March 29

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 L20March 29