1. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
EE5342 – Semiconductor Device Modeling and Characterization Lecture 25 April 19, 2010
Professor Ronald L. Carter

2. MOSFET equivalent circuit elements
Fig 10.51*
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3. n-channel enh. circuit modelG RG
Cgd
RDS
Cgs S RD D
Cbd RB
Cbs
Idrain
Cgb
DSS
DSD RB B
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4. MOS small-signal equivalent circuit
Fig 10.52*
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5. MOSFET circuit parameters
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6. MOSFET circuit parameters (cont)
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7. Substrate bias effect on VT (body-effect)
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8. Body effect data
Fig 9.9**
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9. Fully biased n- channel VT calc

10. Values for fms with silicon gate

11. Q’d,max and xd,max for biased MOS capacitor
Fig 8.11**
|Q’d,max|/q (cm-2)
xd,max (microns)
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12. I-V relation for n-MOS ohmic ID non-physical ID,sat saturated VDS,sat

13. MOS channel- length modulation
Fig 11.5*
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14. Analysis of channel length modulation

15. Channel length mod- ulated drain char
Fig 11.6*
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16. Associating the output conductanceID
ID,sat
VDS,sat
VDS
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17. MOSFET circuit parameters
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18. Estimating LAMBDA
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19. n-channel enhancement MOSFET in ohmic region
0< VT< VG
e- channel ele + implant ion
Channel
VS = 0
0< VD< VDS,sat
EOx,x> 0 n+
e-e- e- e- e- n+
Depl Reg
p-substrate
Acceptors
VB < 0
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20. Subthreshold conduction
Below O.S.I., when the total band-bending < 2|fp|, the weakly inverted channel conducts by diffusion like a BJT.
Since VGS>VDS, and below OSI, then Na>nS >nD, and electr diffuse S --> D
Electron concentration at Source
Concentration gradient
driving diffusion
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21. Subthreshold current data
Figure 10.1**
Figure 11.4*
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22. Mobility variation due to Edepl
Figures 11.7,8,9*
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23. Velocity saturation effects
Figure 11.10*
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24. SPICE mosfet Model Instance CARM*, Ch. 4, p. 290
L = Ch. L. [m]
W = Ch. W. [m]
AD = Drain A [m2]
AS = Source A[m2]
NRD, NRS = D and
S diff in squares
M = device multiplier
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25. CARM*, Ch. 4, p. 99
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26. SPICE mosfet model levels
Level 1 is the Schichman-Hodges model
Level 2 is a geometry-based, analytical model
Level 3 is a semi-empirical, short-channel model
Level 4 is the BSIM1 model
Level 5 is the BSIM2 model, etc.
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27. SPICE Parameters Level 1 - 3 (Static)

28. SPICE Parameters Level 1 - 3 (Static)
* 0 = aluminum gate, 1 = silicon gate opposite substrate type, 2 = silicon gate same as substrate.
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29. SPICE Parameters Level 1 - 3 (Q & N)

30. Level 1 Static Const. For Device Equations
Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni) q*NSS*TOX/eOx
VTO = as given, or
= Vfb + PHI + GAMMA*sqrt(PHI)
KP = as given, or
= UO*eOx/TOX
CAPS are spice pars., technological constants are lower case
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31. Level 1 Static Const. For Device Equations
b = KP*[W/(L-2*LD)] = 2*K, K not spice
GAMMA = as given, or
= TOX*sqrt(2*eSi*q*NSUB)/eOx
2*phiP = PHI = as given, or
= 2*Vt*ln(NSUB/ni)
ISD = as given, or = JS*AD
ISS = as given, or = JS*AS
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32. Level 1 Static Device Equations
vgs < VTH, ids = 0
VTH < vds + VTH < vgs,
id = KP*[W/(L-2*LD)]*[vgs-VTH-vds/2]
*vds*(1 + LAMBDA*vds)
VTH < vgs < vds + VTH,
id = KP/2*[W/(L-2*LD)]*(vgs - VTH)^2
*(1 + LAMBDA*vds)
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33. SPICE Parameters Level 2

34. SPICE Parameters Level 2 & 3

35. Level 2 Static Device Equations
Accounts for variation of channel potential for 0 < y < L
For vds < vds,sat = vgs - Vfb - PHI
+ g2*[1-sqrt(1+2(vgs-Vfb-vbs)/g2]
id,ohmic = [b/(1-LAMBDA*vds)]
*[vgs - Vfb - PHI - vds/2]*vds
-2g[vds+PHI-vbs)1.5-(PHI-vbs)1.5]/3
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36. Level 2 Static Device Eqs. (cont.)
For vds > vds,sat
id = id,sat/(1-LAMBDA*vds)
where id,sat = id,ohmic(vds,sat)
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37. Level 2 Static Device Eqs. (cont.)
Mobility variation
KP’ =
KP*[(esi/eox)*UCRIT*TOX
/(vgs-VTH-UTRA*vds)]UEXP
This replaces KP in all other formulae.
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38. SPICE Parameters Level 3

39. References
CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995.
M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993.
**M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986.
*Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997
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