Dr. Tassadaq Hussain www.tassadaq.ucerd.com Introduction to Verilog – Part-4 Expressing FSM in Verilog (contd) and FSM State Encoding Dr. Tassadaq Hussain www.tassadaq.ucerd.com

Modeling Finite State Machines

General Model of a Digital System DATAPATH – Collection of functional units that process data Functional units are ultimately implemented as combinational and sequential logic CONTROLLER – Coordinates the operations in the datapath Controller (Usually a Finite State Machine) System Control Inputs System Control Outputs Datapath Control Signals Datapath Status Signals System Data Inputs Datapath System Data Outputs

Review: Moore vs Mealy Which is a Moore FSM and which is Mealy FSM? State INPUTS / Next State Combinational Logic Output Combinational / Logic D Q D Q / D Q / OUTPUTS / State INPUTS Next State Combinational Logic Output Combinational / Logic / D Q / D Q D Q / OUTPUTS /

Review: Moore Finite State Machine Output signals depend only on the current state Also, observe the THREE distinct parts State INPUTS / Next State Combinational Logic Output Combinational / Logic D Q / D Q D Q / OUTPUTS / Example State Diagram of a Moore FSM A = 0 A = 0 A = 0 A = 1 SA [F = 0] SB [F = 1] A = 1 SC [F = 1] SD [F = 0] A = 0 A = 1 A = 1 FSM A F

Review: Mealy Finite State Machine Output signals depend on both current state and current inputs Also, observe the THREE distinct parts State INPUTS Output Combinational / Logic / Next State Combinational Logic D Q / D Q D Q / OUTPUTS /

Moore-type FSM Example 3-states FSM Input = w Output = z

Recipe for Describing FSM in Verilog Define the state codes as parameters to list all states from your state diagram. Declare a reg [log2(num states) wide] to store the current state (flip-flops) and next state. Next-state logic: Write one always block to specify the values that next state should have for each value of present state: This is a combinational process (Type-1) Inputs are the current_state (outputs from the first process), and FSM Inputs Use CASE to specify next state Outputs are the FSM outputs Present-state Advancement: Write second always block which specifies that present state is assigned the value of next state on the positive clock edge: This is a sequential process (Type 2 or 3) Inputs to this always block are clock and async reset (if any) Output is the current state signal Output Logic: Write a third always block (optional) that drives the output based on present state (and input in case of Mealy). This is a combinational process (Type-1). Alternatively, can be modeled through continuous statements.

1 2 3 4 5 module moore (Clock, w, Resetn, z); input Clock, w, Resetn; output z; parameter A = 2'b00, B = 2'b01, C = 2'b10; reg [1:0] p_state, n_state;   always @(w, p_state) begin case (p_state) A: if (w = = 0) n_state = A; else n_state = B; B: if (w = = 0) n_state = A; else n_state = C; C: if (w = = 0) n_state = A; default: n_state = 2'bxx; endcase end always @(posedge Clock, negedge Resetn) if (Resetn = = 0) p_state <= A; else p_state <= n_state; assign z = (p_state = = C); endmodule  1 2 3 4 5

Combining Next Sate Logic and Output Logic module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;   // Define the next state combinational circuit always @(w, y) begin case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; C: if (w) Y = C; default: Y = 2'bxx; endcase z = (y = = C); //Define output end // Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; endmodule

Alternate Coding Style 3 – One Always block module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;   // Define the sequential block always @(negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C; C: if (w) y <= C; default: y <= 2'bxx; endcase // Define output assign z = (y = = C); endmodule

Which Coding Style do I opt for my FSM? While all the three coding styles yield the same functionally equivalent FSM: It is suggested to stick with the first style, i.e. three always blocks (recall that third output logic block is optional); More closer to the circuit description Easier to read and debug

Impact of State Encoding on Sequential Circuit Complexity

Derivation for Next-state and Output Logic Expressions y y 2 1 Ignoring don't cares Using don't cares w 00 01 11 10 d Y = wy y Y = wy y 1 1 2 1 1 2 1 1 d y y 2 1 w 00 01 11 10 d Y = wy y + wy y Y = wy + wy 2 1 2 1 2 2 1 2 1 1 d 1 = w ( y + y ) 1 2 y 1 y 2 1 z = y y z = y 1 2 2 1 1 d

Final Implementation

State Encoding Fewer Gates  Lesser Implementation Cost Y y D Q z Q Y 2 2 D Q z Q Y y 1 1 w D Q Clock Q Resetn Fewer Gates  Lesser Implementation Cost

Other State-Encoding Options One-Hot: Another interesting possibility is to use as many state variables as there are states. In this method, for each state all but one of the state variables are equal to 0. The variable whose value is 1 is deemed to be “hot.” The approach is known as the one-hot encoding method. Two-Hot: Two variables are 1 in any given state. Johnson: Output of Johnson counter is used to encode the states, complement output of the last flip-flop Q̅n is back-fed to the first flip-flop in the chain.

Choosing THE Best State Encoding In general, circuits are much larger than our example, and different state assignments can have a substantial effect on the cost of the final implementation. It is often impossible to find the best state assignment for a large circuit. CAD tools usually perform the state assignment using heuristic techniques (https://en.wikipedia.org/wiki/Heuristic): These techniques are usually proprietary, and their details are seldom published.

Specifying the State Encoding in an EDA Tool Verilog compilers usually have a capability to search for different assignments that may give better results: such as attempting to use the one-hot encoding etc. The user can either allow the compiler to use its FSM-handling capability, or suppress it in which case the compiler simply deals with the Verilog statements in the usual way. In Quartus Prime: Assignments  Settings  Compiler Settings  Advanced Settings (Synthesis)  Filter with keyword ‘state’  State machine processing

Specifying State Encoding in Intel Quartus Prime

Recommended Reading Stephen Brown - Fundamentals of Digital Logic with Verilog Design, 3rd Edition: Chapter-5: 5.12 and 5.13 Chapter-6: 6.1 – 6.4. Also pay attention to FSM examples.

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