1. Introduction to Verilog – Part-2 Procedural Statements
Dr. Tassadaq Hussain

2. Verilog Procedural Statements
[begin]
[procedural assignment statements]
[if-else statements]
[case statements]
[while, repeat, and for loops]
[task and function calls]
[end]
Verilog syntax requires that procedural statements be contained inside a construct called an always block.

3. About Always block An always block represents a hardware block in HW.
A typical Verilog design module may include several always blocks
each representing a part of the circuit being modeled.
all the always blocks are concurrent with respect to one another.
insert synthesis snapshot 3

4. Always block Sensitivity List
The part of the always block after in parentheses, is called the sensitivity list.
The sensitivity list simply tells the Verilog compiler which signals can directly affect the outputs produced by the always block.
More simply can be written as,
Tells the compiler to include all input signals in the sensitivity list 4

5. Statement Order is IMPORTANT inside an Always Block
An important property of the always block is that the statements it contains are evaluated in the order given in the code:
This is in contrast to the continuous assignment statements,
which are evaluated concurrently and hence have no
meaningful order.
Stay tuned for an example.

6. Procedural Assignment Statements
Any signal assigned a value inside an always block has to be a variable of type reg or integer.
There are two kinds of assignments in an Always block:
Blocking assignments, denoted by the = symbol
Non-blocking assignments, denoted by the <= symbol.
Blocking procedural assignment “=“
The term blocking means that the assignment statement completes and updates its left-hand side before the subsequent statement is evaluated;
e.g., Assume A holds the value 1 … A=2; B=A; A is left with 2, B with 2.
Non-blocking procedural assignment “<=“
RHS is executed and assignment takes place at the end of the current time step
e.g., Assume A holds the value 1 … A<=2; B<=A; A is left with 2, B with 1.

7. Blocking vs Non-Blocking: Avoid Confusion
Notion of “current time step” is tricky in synthesis, so to guarantee that your simulation matches the behavior of the synthesized circuit, follow these rules:
Use blocking assignments to model combinational logic within an always block.
Use non-blocking assignments to implement sequential logic.
Do not mix blocking and non-blocking assignments in the same always block.
It is not possible to model both a combinational output and a sequential output in a single always block.
Do not make assignments to the same variable from more than one always block

8. Procedural Statement: If-Else

9. Example: Statement Ordering inside an Always block
module mux (w0, w1, s, f);
input w0, w1, s;
output reg f;
w1, s)
begin
f = w0;
if (s == 1)
f = w1;
end
endmodule
module mux (w0, w1, s, f);
input w0, w1, s;
output reg f;
w1, s)
begin
if (s == 1)
f = w1;
f = w0;
end
endmodule
Insert or show synthesis result here
Still a MUX
Not a MUX Anymore
Verilog semantics specify that a signal assigned multiple values in an always construct retains the last assignment. 9

10. Procedural Statement: The Case
(expression)
The bits in expression, called the controlling expression, are checked for a match with each alternative.
alternative1:
begin
statement;
end
alternative2:
begin
statement;
end
[default :
begin
statement;
end]
endcase

11. Case: Example module mux (w0, w1, s, f); input w0, w1, s;
output reg f;
w1, s)
case (s)
1’b0: f = w0;
1’b1: f = w1;
endcase 
endmodule

12. Using a Case to Specify a Truth-Table
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output reg s, Cout;
x, y)
begin
case ( {Cin, x, y} )
3'b000: {Cout, s} = 'b00;
3'b001: {Cout, s} = 'b01;
3'b010: {Cout, s} = 'b01;
3'b011: {Cout, s} = 'b10;
3'b100: {Cout, s} = 'b01;
3'b101: {Cout, s} = 'b10;
3'b110: {Cout, s} = 'b10;
3'b111: {Cout, s} = 'b11;
endcase
end
endmodule

13. Procedural Statement: Loop(s)
Verilog includes four types of loop statements:
for
while
repeat
forever
Synthesis tools typically support the for loop, which has the general form:
for (initial_index; terminal_index; increment)
begin
statement;
end

14. Example: for Loop x y x y x y c c c FA c c FA FA s s s MSB position1 n – 1 1 1 c 1 c c FA c c n n ” 1 FA FA 2 s s s n – 1 1
MSB position
LSB position

15. Example: for Loop module ripple (carryin, X, Y, S, carryout);
parameter n = 4;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout;
reg [n:0] C;
integer k;
Y, carryin)
begin
C[0] = carryin;
for (k = 0; k <= n-1; k = k+1)
S[k] = X[k] ^ Y[k] ^ C[k];
C[k+1] = (X[k] & Y[k]) | (C[k] & X[k]) | (C[k] & Y[k]);
end
carryout = C[n];
endmodule

16. Recommended Reading/Practice
Stephen Brown - Fundamentals of Digital Logic with Verilog Design:
Chapter-4: 4.6 – Verilog for Combinational Circuits
Give practice labs, uploaded on LMS, a try to check out your skills.

17. THANK YOU 17