Supplement on Verilog combinational circuit examples

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Presentation transcript:

Supplement on Verilog combinational circuit examples Based on Fundamentals of Digital Logic with Verilog Design By Brown/Vranesic 3rd. Chung-Ho Chen

Conditional Execution A MuX: Form 1 A = (x1< x2)? (B+1): (B); If x1 < x2, A = B+1, else A = B; module mux_2to1 (x0, x1, s, f); input x0, x1, s; output f; assign f = s ? x1 : x0; endmodule A MuX: Form 2 module mux_2to1 (x0, x1, s, f); input x0, x1, s; output reg f; always @(x0, x1, s) f = s ? x1 : x0; endmodule Continuous assignment always block

Conditional Execution A = (x1< x2)? (B+1): (B); If x1 < x2, A = B+1, else A = B; A MuX: Two conditional bits declared in vectored signal module mux_4to1 (x0, x1, x2, x3, S, f); input x0, x1, x2, w3; input [1:0] S; output f; assign f = S[1] ? (S[0] ? x3 : x2) : (S[0] ? x1 : x0); endmodule f s 1 x 00 01 2 3 10 11 First see if s1 is 1, if true, then if s0 is true: then f = x3

Conditional Execution using if else 2to1 MuX module mux_2to1 (x0, x1, s, f); input x0, x1, s; output reg f; always @(x0, x1, s) if (s==0) f = x0; else f = x1; endmodule module mux_2to1 (x0, x1, s, f); input x0, x1, s; output reg f; always @(x0, x1, s) f = s ? x1 : x0; endmodule

Conditional Execution Using case module mux_4to1 (x, s, f); input [0:3] x; input [1:0] s; output reg f; always @(x, s) case (s) 0: f = x[0]; 1: f = x[1]; 2: f = x[2]; 3: f = x[3]; endcase endmodule module mux_2to1 (x0, x1, s, f); input x0, x1, s; output reg f; always @(x0, x1, s) if (s==0) f = x0; else f = x1; endmodule 2’b00

Signal states: 0, 1, z, or x High impedance state z: output behaves like an open circuit and not connected to any defined voltage value. Don’t care state x: does not matter whether a given logic variable has the value of 0 or 1.

Example of using casex d 1 U y z x U3 has the highest priority. module priority (U, Y, z); input [3:0] U; output reg [1:0] Y; output reg z; always @(U) begin z = 1; casex (U) 4'b1xxx: Y = 3; 4'b01xx: Y = 2; 4'b001x: Y = 1; 4'b0001: Y = 0; default: begin z = 0; Y = 2'bx; end endcase endmodule d 1 U y z x 2 3 U3 has the highest priority.

Verilog Operators A[2:0], B[2:0]; f, w is scalar & 1 x | ^ ~ ^ Bitwise AND Bitwise OR A[2:0], B[2:0]; f, w is scalar 1. f = A & B, (bitwise and) only the least significant bits are involved, ie, f = A[0] & B[0]; 2. f = !A; f = 1 only if all bits in A are 0, ie, f = ~(a2 +a1 +a0). f = A && B; f=(a2+a1+a0) . (b2+b1+b0) f =&A; f = a2.a1.a0. (reduction and) Concatenate and Replication: {3{A}}= {A,A,A} = a2a1a0a2a1a0a2a1a0 & 1 x | ^ ~ ^ Bitwise XOR Bitwise XNOR

Using Task in Verilog Task: circuit routine for replication 4 Inputs of 16to1 Task: circuit routine for replication Output of a task must be a variable. The task must be included in the module that calls it. A task can call another task and it may invoke a function.

Using Function in Verilog Function: circuit function for invocation Return a single value which is placed where the function is invoked. A function can call other function but cannot call a task. Input Return one of the inputs (W12-15)