Introduction to Computer Architecture Dr. Hadi AL Saadi Faculty Of Information Technology University of Petra 4/7/2019 Dr. Hadi Hassan Computer architecture

Which Books will be Used? Computer Organization & Design The Hardware/Software Interface David Patterson and John Hennessy Morgan Kaufmann Publishers Fourth Edition (2012) Read the textbook in addition to the course slides References: MIPS32 Architecture Volumes I, II, and III are available online For more information about MIPS please visit https://www.youtube.com/watch?v=u5Foo6mmW0I&index=1&list=PL5b07qlmA3P6zUdDf-o97ddfpvPFuNa5A

What is Computer Architecture? The science and art of designing, selecting, and interconnecting hardware components and designing the hardware/software interface to create a computing system that meets functional, performance, energy consumption, cost, and other specific goals. Software Application Trends Operating System Application (AI,DB Graphics ) Programming Language, complier How does an assembly program end up executing as digital logic? What happens in-between? How is a computer designed using logic gates and wires to satisfy specific goals? Architect/ microarchitect’s view: How to design a computer that meets system design goals. Choices critically affect both the SW programmer and the HW designer Instruction Set Architecture (ISA) Microarchitecture System architecture Technology Trends VLSI / Hardware Implementation Hardware 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Why study Computer Architecture ? You want to be called “Computer Scientist” You want to become an “expert” on computer hardware You want to become a “computer system designer” You want to become a “software designer” and need to understand how to improve code performance Technology is improving rapidly  new opportunities Has never been more exciting! Impacts Electrical Engineering and Computer Science 4/7/2019 Dr. Hadi Hassan Computer architecture

Course Learning Outcomes Towards the end of this course, you should be able to … Describe the instruction set architecture of a MIPS processor Analyze, write, and test MIPS assembly language programs Describe organization/operation of integer & floating-point units Design the datapath and control of a single-cycle CPU Describe the organization/operation of memory and caches Analyze the performance of processors and caches Required Background Ability to program confidently in Java or C 4/7/2019 Dr. Hadi Hassan Computer architecture

Some Important Questions to Ask What is Assembly Language? What is Machine Language? How is Assembly related to a high-level language? Why Learn Assembly Language? What is an Assembler, Linker, and Debugger? 4/7/2019 Dr. Hadi Hassan Computer architecture

A Hierarchy of Languages Application Programs High-Level Languages Assembly Language Machine Language Hardware High-Level Language Low-Level Language Machine independent Machine specific 4/7/2019 Dr. Hadi Hassan Computer architecture

Assembly and Machine Language Native to a processor: executed directly by hardware Instructions consist of binary code: 1s and 0s Assembly language Slightly higher-level language Readability of instructions is better than machine language One-to-one correspondence with machine language instructions Assemblers translate assembly to machine code Compilers translate high-level programs to machine code Either directly, or Indirectly via an assembler 4/7/2019 Dr. Hadi Hassan Computer architecture

Compiler and Assembler 4/7/2019 Dr. Hadi Hassan Computer architecture

Translating Languages Program (C Language): swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } A statement in a high-level language is translated typically into several machine-level instructions MIPS Assembly Language: sll $2,$5, 2 add $2,$4,$2 lw $15,0($2) lw $16,4($2) sw $16,0($2) sw $15,4($2) jr $31 Compiler MIPS Machine Language: 00051080 00821020 8C620000 8CF20004 ACF20000 AC620004 03E00008 Assembler 4/7/2019 Dr. Hadi Hassan Computer architecture

Advantages of High-Level Languages Program development is faster High-level statements: fewer instructions to code Program maintenance is easier For the same above reasons Programs are portable Contain few machine-dependent details Can be used with little or no modifications on different machines Compiler translates to the target machine language However, Assembly language programs are not portable 4/7/2019 Dr. Hadi Hassan Computer architecture

Why Learn Assembly Language? Many reasons: Accessibility to system hardware Space and time efficiency Writing a compiler for a high-level language Assembly Language is useful for implementing system software Also useful for small embedded system applications Space and Time efficiency Understanding sources of program inefficiency Tuning program performance Writing compact code 4/7/2019 Dr. Hadi Hassan Computer architecture

Assembly Language Programming Tools Editor Allows you to create and edit assembly language source files Assembler Converts assembly language programs into object files Object files contain the machine instructions Linker Combines object files created by the assembler with link libraries Produces a single executable program Debugger Allows you to trace the execution of a program Allows you to view machine instructions, memory, and registers 4/7/2019 Dr. Hadi Hassan Computer architecture

Assemble and Link Process Source File Assembler Object Linker Executable Link Libraries A program may consist of multiple source files Assembler translates each source file separately into an object file Linker links all object files together with link libraries 4/7/2019 Dr. Hadi Hassan Computer architecture

MARS Assembler and Simulator Tool 4/7/2019 Dr. Hadi Hassan Computer architecture

Components of a Computer System Processor Datapath Control Memory & Storage Main Memory Disk Storage Input devices Output devices Bus: Interconnects processor to memory and I/O Network: newly added component for communication Computer Memory I/O Devices Input Output BUS Control Datapath Processor Disk Network 4/7/2019 Dr. Hadi Hassan Computer architecture

Inside the Processor (CPU) Datapath: part of a processor that executes instructions Control: generates control signals for each instruction Clock Next Program Counter Control Instruction Cache Registers A L U Data Cache Program Counter Instruction 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Datapath Components Program Counter (PC) Contains address of instruction to be fetched Next Program Counter: computes address of next instruction Instruction and Data Caches Small and fast memory containing most recent instructions/data Register File General-purpose registers used for intermediate computations ALU = Arithmetic and Logic Unit Executes arithmetic and logic instructions Buses Used to wire and interconnect the various components 4/7/2019 Dr. Hadi Hassan Computer architecture

Programmer’s View of a Computer System Application Programs High-Level Language Assembly Language Operating System Instruction Set Architecture Microarchitecture Physical Design Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Increased level of abstraction Each level hides the details of the level below it Software Hardware Interface SW & HW 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Programmer's View – 2 Application Programs (Level 5) Written in high-level programming languages Such as Java, C++, Pascal, Visual Basic . . . Programs compile into assembly language level (Level 4) Assembly Language (Level 4) Instruction mnemonics are used Have one-to-one correspondence to machine language Calls functions written at the operating system level (Level 3) Programs are translated into machine language (Level 2) Operating System (Level 3) Provides services to level 4 and 5 programs Translated to run at the machine instruction level (Level 2) 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Programmer's View – 3 Instruction Set Architecture (Level 2) Interface between software and hardware Specifies how a processor functions Machine instructions, registers, and memory are exposed Machine language is executed by Level 1 (microarchitecture) Microarchitecture (Level 1) Controls the execution of machine instructions (Level 2) Implemented by digital logic Physical Design (Level 0) Implements the microarchitecture Physical layout of circuits on a chip 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture The Von Neumann Model/Architecture Model for designing and building computers, based on the following three characteristics: The computer consists of four main sub-systems: Memory ALU (Arithmetic/Logic Unit) Control Unit Input/Output System (I/O) Program is stored in memory during execution. Program instructions are executed sequentially. 4/7/2019 Dr. Hadi Hassan Computer architecture

The Von Neumann Architecture Bus Memory Processor (CPU) Input-Output Control Unit Communicate with "outside world", e.g. Screen Keyboard Storage devices ... Store data and program Execute program ALU Do arithmetic/logic operations requested by program 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture The Von Neumann Model/Architecture Von Neumann model: An instruction is fetched and executed in control flow order As specified by the instruction pointer Sequential unless explicit control flow instruction 4/7/2019 Dr. Hadi Hassan Computer architecture

Infinite Cycle implemented in Hardware Fetch - Execute Cycle Fetch instruction Compute address of next instruction Instruction Fetch Instruction Decode Generate control signals for instruction Read operands from registers Execute Infinite Cycle implemented in Hardware Compute result value Memory Access Read or write memory (load/store) Writeback Result Writeback result in a register 4/7/2019 Dr. Hadi Hassan Computer architecture

Dataflow Model/Architecture Dataflow model: An instruction is fetched and executed in data flow order i.e., when its operands are ready i.e., there is no instruction pointer Instruction ordering specified by data flow dependence Each instruction specifies “who” should receive the result An instruction can “fire” whenever all operands are received Potentially many instructions can execute at the same time Inherently more parallel 4/7/2019 Dr. Hadi Hassan Computer architecture

Von Neumann vs Dataflow Consider a von Neumann program What is the significance of the program order? What is the significance of the storage locations? Which model is more natural to you as a programmer? + *2 - * a b z Dataflow v <= a + b; w <= b * 2; x <= v - w y <= v + w z <= x * y Sequential 4/7/2019 Dr. Hadi Hassan Computer architecture

Instruction Set Architecture (ISA) “Instruction Set Architecture is the structure of a computer that a machine language programmer (or a compiler) must understand to write a correct (timing independent) program for that machine.”, or its Critical interface between hardware and software The ISA defines: – Operations that the processor can execute – Data Transfer mechanisms + how to access data – Control Mechanisms (branch, jump, etc) – “Contract” between programmer/compiler + HW 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Classifying of ISAs 1- Stack–based architecture • Architectures with implicit “stack” – Acts as source(s) and/or destination, TOS is implicit – Push and Pop operations have 1 explicit operand Instructions PUSH B /* store data in address B in stack top */ POP B /* load data in stack top to address B */ ADD /* stack top= stack top + [stacktop-1] */ SUB /* stack top= stack top - [stacktop-1]*/ MUL /* stack top= stack top * [stacktop-1]*/ DIV /* stack top= stack top / [stacktop-1]*/ 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Example Write instructions for the following C statement using Stack–based architecture. F =A * B - ( C * D +E); PUSH C PUSH D MUL PUSH E ADD POP T PUSH B PUSH A POP X PUSH T PUSH X SUB POP F 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Accumulator- Based Architecture • Architectures with one implicit register – Acts as source and/or destination – One other source explicit Instructions STA B /* store data in accumulator in address B */ LDA B /* put data in address B in accumulator */ ADDA D /* ACC=ACC+D */ SUBA D /* ACC=ACC-D */ MULA F /* ACC=ACC*F */ DIVA F /* ACC=ACC/F */ 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Example Write the instructions for the following C statement using accumulator –based architecture. F =A * B - ( C * D +E); Solution: LDA C /* put data in address C in accumulator */ MULA D /* Acc=C*D */ ADDA E /* Acc=C*D+E */ STA T /* T=C*D+E */ LDA A /* put data in address A in accumulator */ MULA B /* Acc=A*B */ SUBA T /* Acc=A*B-(C*D+E) */ STA F /* F= A*B-(C*D+E) */ 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture Register- Based Architecture • Most common approach – Fast, temporary storage (small) – Explicit operands (register IDs) • Example: C = A + B Register-memory load/store Load R1, A Load R1, A Add R3 ,R1,B Load R2, B Store R3,C Add R3,R1,R2 Store R3,C • All RISC ISAs are load/store • IBM 360, Intel x86, Moto 68K are register-memory 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture RISC vs. CISC Arguments • RISC ( Reduced Instruction Set Computer ) – Simple Implementation • Load/store, fixed-format 32-bit instructions, efficient pipelines – Lower CPI (Cycle Per Instruction ) – Compilers do a lot of the hard work • MIPS = Microprocessor without Interlocked Pipelined Stages • CISC ( Complex Instruction Set Computer ) – Simple Compilers (assists hand-coding, many addressing modes, many instructions) – Code Density 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture CISC and RISC Instruction set CISC- Complex Instruction Set Computer Memory in those days was expensive bigger program->more storage->more money Hence needed to reduce the number of instructions per program Number of instructions are reduced by having multiple operations within a single instruction Multiple operations lead to many different kinds of instructions that access memory In turn making instruction length variable and fetch-decode-execute time unpredictable – making it more complex Thus hardware handles the complexity Example: x86 ISA 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture CISC- Complex Instruction Set Computer CISC Language Development Increase instruction size of instruction sets (by providing more operations) Design ever more complex instructions Provide more addressing modes Implement some HLL constructs in machine instruction sets 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture CISC- Complex Instruction Set Computer Intel 8086, 80286, 80386, 80486, Pentium The logic for each instruction has to be hard-wired into the control unit As new instructions developed they were added to original instructions set Difficult and expensive to design and build One way of solving this problem is to use microprogramming Microprogramming – complex instructions are split into a series of simpler instructions When a complex instruction is executed, the CPU executes a small microprogram stored in a control memory This simplifies design of processor and allows the addition of new complex instructions 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture RISC- Reduced Instruction Set Computer Attempt to make architecture simpler Reduced number of instructions Make them all the same format if poss. Reduce the number of memory accesses required by increasing the number of registers Reduce the number of addressing modes Allow pipelining of instructions 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture RISC- Reduced Instruction Set Computer The characteristics of most RISC processors are… A large number of GP registers A small number of simple instructions that mostly have the same format A minimal number of addressing modes Optimisation of instruction pipeline 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture CISC and RISC Instruction set CISC processor RISC processor Intel 80486 Sun SPARC Year developed 1989 1987 No. instructions 235 69 Instruction Size (bytes) 1-11 4 Addressing modes 11 1 GP Registers 8 40-520 4/7/2019 Dr. Hadi Hassan Computer architecture

Dr. Hadi Hassan Computer architecture RISC in the Home In your Home : is likely to have many devices with RISC-based processors. Devices using RISC-based processors include the Nintendo Wii, Microsoft Xbox 360, Sony PlayStation3, Nintendo DS and many televisions and phones. However, x86 processors--those found in nearly all of the world's personal computers--are CISC. This is a limitation born of necessity; adopting a new instruction set for PC processors would mean that all the software used in PCs would no longer function. 4/7/2019 Dr. Hadi Hassan Computer architecture

Overview of the MIPS ISA All instructions are 32-bit wide Instruction Categories Load/Store Integer Arithmetic Jump and Branch Floating Point Memory Management Three Instruction Formats R0 - R31 PC HI LO Registers Op6 Rs5 Rt5 Rd5 funct6 sa5 immediate16 immediate26 R-type I-type J-type 4/7/2019 Dr. Hadi Hassan Computer architecture