Computer System Overview B.Ramamurthy Chapter 1 2/25/2019 B.Ramamurthy

Basic Elements Processor: control unit and registers Register : User visible, control and status registers User visible: R0.. R32, data registers, address registers, stack pointer.. Control/status: PC (program counter), IR (Instruction register) Main memory : Instructions and data IO modules (buffer), system interconnection (bus). 2/25/2019 B.Ramamurthy

Instruction Execution A fundamental operation in a processor is instruction execution. Instruction cycle: fetch cycle + execute cycle PC holds the address of the next instruction to be executed. Instruction pointed to by the PC is fetched from main memory into the IR. Instruction is decoded and executed Instruction may be process-memory, processor-IO, data processing, or control/logic 2/25/2019 B.Ramamurthy

Interrupts Normal processing of instructions can be interrupted so that the processor may respond to other events. The mechanism provided for interruption is known as “interrupts”. Interrupts are provided to improve processor efficiency. Types of interrupts: program, timer, IO, hardware failure. 2/25/2019 B.Ramamurthy

Program Flow with and without Interrupts Fig 1.2 2/25/2019 B.Ramamurthy

Instruction Cycle with Interrupts Fig 1.7 2/25/2019 B.Ramamurthy

Interrupt Processing Consider the steps involved in IO interrupt when a device completes IO operation. 1.. CPU initiates IO operation to a device and goes about its normal processing. 2. Device completes IO and sends interrupts signal to the processor. 3. Processor completes current instruction before responding to the interrupt. 4. Processor determines the source of interrupt and sends acknowledgement. 5. Processor them saves its current state and transfers control to interrupt handler. 2/25/2019 B.Ramamurthy

Interrupt Processing (contd.) 6. Interrupt handler (or interrupt service routine - ISR) completes executiona d returns control to the main routine by restoring the saved context from step 5. 7. Processor resumes its normal processing. 2/25/2019 B.Ramamurthy

Multiple Interrupts An interrupt may occur during the processing of another interrupt. This may lead to nested interrupt handling. This is permitted in many situations. But it is also possible to control the response to interrupts by masking certain interrupts and by disabling interrupts. Interrupts are useful not only in IO processing but also in multiprogramming. 2/25/2019 B.Ramamurthy

IO Communication Programmed IO Interrupt-driven IO Direct Memory Access Fig. 1.19 2/25/2019 B.Ramamurthy

Direct Memory Access IO <--> Memory is controlled by DMA unit. DMA unit issues read and write cycles and is in control of the bus. This process is called “cycle stealing”. For block transfers DMA is far more efficient than interrupt driven IO. 2/25/2019 B.Ramamurthy

Summary Instruction cycle, interrupts, basic IO are fundamental processor operation. We will look into memory related details in a later discussion. 2/25/2019 B.Ramamurthy