PML Semiconductor Electronics Division, NIST

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Group Members: ADIL KHAN MEHMAL JAVED
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Presentation transcript:

PML Semiconductor Electronics Division, NIST Application of Time-Domain Reflectometry To Detect Interconnect Failures -Binayak Kandel Mentors Dr. Yaw Obeng Dr. Chukwudi Okoro PML Semiconductor Electronics Division, NIST

Outlines Introduction Project Goal Procedure Conclusion How far we have come? 3-D stacking and Interconnects Project Goal Procedure Conclusion

How Far Have We Come? Electronic Numerical Integrator And Computer (ENIAC) -1946 17,468 vacuum tubes ~1800 square feet ~150 kW of power -This led to a rumor that whenever the computer is switched ON, lights in Philadelphia dimmed. http://www.fi.edu/learn/case-files/eckertmauchly/team.html

How Far Have We Come? Ivy Bridge Processors -2012 1.4 billion transistors (Tri “3-D” Transistors) 160 mm2 die size 50% less power consumption than its predecessor. -50% less power consumption at the same consumption level as 2-D planer transistors http://www.digitaltrends.com/computing/getting-ready-to-cross-ivy-bridge-the-laymans-guide-to-intels-latest-processors/

3-D Stacking Advantages: Increased portability Increased Functionality TSV Connections Advantages: Increased portability Increased Functionality Increased Transmission Speed IBMs new 3D manufacturing technology

Through-Silicon Via (TSV) Interconnects Back-End-of-Line(BEOL) Connects individual components like transistors and capacitors Through-Silicon Via(TSV) Vertical connections that pass through wafer or die Through-Silicon Via (TSV) Talk abt NIST at the end of this slide ..But the reliability of these interconnects are not studied well enough 6

Reliability Challenges of TSV Void occurred at the bottom of TSV, on the connecting Cu pad due to electromigration What is electromigration? It is just one of the causes of the void formation Deformation or voids means it *Y.C. Tan et al, Electromigration performance of Through Silicon Via (TSV) – A modeling approach **T. Frank et al, IRPS, 2011

Reliability Challenges Contd…. Rambient = 13.3xx Ω Rinitial = 26.3xx Ω Rfinal = 30.6xx Ω FAILURE V = I*R…same current applied but voltage increased exponentially. That means Resistance increased. …How do we find out the location of these failures?

Project Goal Determine the failure locations in interconnects using Time-Domain Reflectometry (TDR)

TDR Works on the same principle as radar TDR transmits a short rise time pulse along the conductor. Any discontinuities in the impedance causes signal to reflect back. Discontinuities Time Amplitude T D = Distance vρ = Velocity of Propagation T = Time

Why TDR (1)? Easy and accurate to locate failures like open termination or any kind of discontinuities. Daeil et al ,Early Detection of Interconnect Degradation using RF Impedance 2008

Why TDR (2)? Non destructive method to pinpoint failures Daeil et al ,Early Detection of Interconnect Degradation using RF Impedance 2008

Reliability Challenges Contd…. Rambient = 13.3xx Ω Rinitial = 26.3xx Ω Rfinal = 30.6xx Ω FAILURE V = I*R…same current applied but voltage increased exponentially. That means Resistance increased. …How do we find out the location of these failures in the sea of TSVs? Use TDR.

My Task Prepare sample Learn to use LeCroy WaveExpert 100h Take TDR measurements Locate where failure occurred Correlate data measured from Vector Network Analyzer (VNA) with the TDR data Test Sample LeCroy WaveExpert 100h 14 S. Vahanen et al, 3D integration activities at CERN 2010

Acknowledgement Society of Physics Students Entire SPS and AIP Family National Institute of Standards and Technology(NIST) Dr. David Seiler, Dr. Yaw Obeng, Dr. Chukwudi Okoro, Dr. John Suehle Dr. Yaqub Afridi Entire PML Semiconductor and Electronics Division Family Fellow Summer Interns

Thank You!