Etch Factor Impact on SI&PI (*) Samtec, (**) Ansys, (***) Oracle Gustavo Blando(*), Rula Bakleh(*), Jim DeLap(**), Scott McMorrow(*), Ethan Koether(***), Istvan Novak(*) (*) Samtec, (**) Ansys, (***) Oracle Presented as part of the DesignCon 2019 Conference and Expo. For more information on the event, please go to DesignCon.com

Etch Factor Impact on SI & PI Gustavo Blando, (Samtec) Rula Bakleh (Samtec), Jim DeLap (Ansys), Scott McMorrow (Samtec), Ethan Koether (Oracle), Istvan Novak (Samtec) January 29 – 31, 2019

Speaker Gustavo Blando Senior Principle Engineer, Samtec Gustavo.blando@samtec.com Gustavo Blando is a Senior Principle Engineer leading the Principal SI/PI Architect at Samtec Inc. In addition to his leadership roles, he's charged with the development of new SI/PI methodologies, high speed characterization, tools and modeling in general. Gustavo has twenty plus years of experience in Signal Integrity and high speed circuits. January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

Introduction Why etch factor may matter One-ounce copper Two-ounce copper Wet etching process creates slanted copper walls Non-vertical walls may alter Trace impedance Crosstalk Plane resistance Resist Resist Foil Core January 29 – 31, 2019

Introduction Note: a and V/X are not directly related Etch factor definition The PCB industry’s metric is the V/X etch factor IPC-2221 definition For the SI and PI engineers it is the a angle that matters Ideal vertical side walls Slanted side walls Note: a and V/X are not directly related January 29 – 31, 2019

Introduction Stackup dependence Typical wet etching process leaves wider copper facing the carrier dielectric, which is: Core for inner layers, or the board on outer layers January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

Baseline Simulations 2D geometry and characteristic impedance Slanted trace walls change characteristic impedance How does it change each of the RLGC parameters? January 29 – 31, 2019

Baseline Simulations 2D geometry and characteristic impedance Slanted trace walls increase impedance Frequency domain Time domain α January 29 – 31, 2019

Baseline Simulations 2D, RLGC parameters Approximately 3% variation Slanted trace walls lower capacitance, and increase inductance Inductance versus frequency Capacitance versus frequency +/- 2%, L goes up C goes down same proportion such tpd = constant in strip line Rectangular Trapezoidal (45) Rectangular Trapezoidal (45) January 29 – 31, 2019

Baseline Simulations 2D, RLGC parameters Slanted trace walls increase resistance Conductance varies with due to capacitance Resistance versus frequency Conductance versus frequency (+/-3.5%) G = tand * C * w (+/-2% as C) Relative resistance change is negative: With 45-degree walls perimeter is 17% lower resistance increase is only 6% Rectangular Trapezoidal (45) Rectangular Trapezoidal (45) January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

Routing Under a BGA 2D simplified view Odd-Mode Worst-case bound Current crowding (proximity effect) Odd-Mode Worst-case bound E field 4-mil shift Left: trace over void Asymmetrical fields January 29 – 31, 2019

Routing Under a BGA RLGC Slanted trace walls decrease capacitance and increase inductance at higher frequencies Inductance versus frequency Capacitance versus frequency Low frequency current re-distribution, more plane to go about!!!!! January 29 – 31, 2019

Routing Under a BGA RLGC Conductance versus frequency Resistance versus frequency January 29 – 31, 2019

Routing Under a BGA RLGC Rectangle vs. Trapezoidal comparison: Around 5% in inductance Around 7% in resistance Very little difference between centered or offset traces in deltas. January 29 – 31, 2019

Routing Under a BGA RLGC Rectangle vs. Trapezoidal comparison: Around 5% in capacitance and conductance, they follow each other Very little difference between centered or offset traces in deltas. January 29 – 31, 2019

Routing Under a BGA Losses Traces centered 20” Line: Small difference in IL (simple renormalization masks this small difference) January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

Etch Factor Over Perforation Real case Realistic 3D geometry Differential trace pair 2x or 4x antipads Simulation goals Impedance Loss Crosstalk Risk: Undesired reflections when concatenating January 29 – 31, 2019

Etch Factor Over Perforation Impedance over perforated planes Vertical side wall 45-degree side wall X2 unit cell 10ps TDR edge 2 Ohm difference January 29 – 31, 2019

Etch Factor Over Perforation Impedance change over perforated planes Change of impedance difference due to etch factor January 29 – 31, 2019

Etch Factor Over Perforation Vertical crosstalk Vertical crosstalk through antipad opening January 29 – 31, 2019

Etch Factor Over Perforation Vertical crosstalk vs. horizontal offset Simple renormalization will change the order. Offset No perceived effect January 29 – 31, 2019

Etch Factor Over Perforation Concatenated cells ? ? ? ? ? January 29 – 31, 2019

Why this looks so ugly (1) ?? Concatenated cells 1.64mm 2.00mm air When the traces are centered, we only see a glimpse of it Half wave plane resonances ? January 29 – 31, 2019

Why this looks so ugly (2) ?? Concatenated cells Going to treat it as a diff-pair Different Modal Propagation delay (length dependent) Even with homogeneous dielectric (non uniform line) Single Ended IL: Dips are when ODD becomes EVEN and vice-versa: 1/(2*delta_tpd) Unit cell approach (treat it with care!!!) http://electrical-integrity.com/Paper_download_files/DC07_SUN_difflosses_v14.pdf January 29 – 31, 2019

Differential vs. Common Mode Field Distributions (Delay) January 29 – 31, 2019

Etch factor Over Perforation Concatenated cells January 29 – 31, 2019

OUTLINE Introduction Baseline simulations Why etch factor may matter Etch factor definitions, back to basics Baseline simulations Geometry and characteristic impedance RLGC parameters Routing under a BGA; 2D simplification Geometry and fields Etch factor over perforation; real case 3D geometry Impedance over perforated planes Vertical crosstalk DC effect in perforated planes Geometry and definition of DC resistance Resistance of perforated planes Unit cell and results Array of 9x9 antipads Summary and conclusions January 29 – 31, 2019

DC Effect in Perforated Planes Geometry and definition Same assumptions for sheet resistance on plane calculation Simple geometries: Underlying assumption: (uniform cross-sectional current distribution) Generic resistance formula: Generic formula on Ansys Q3D-Extract DC solver (without current distribution assumption) January 29 – 31, 2019

DC Effect in Perforated Planes Resistance Heavier copper leaves less copper on top Parameterized unit cell January 29 – 31, 2019

DC Effect in Perforated Planes Resistance vs. sheet thickness Th=0.1 4oz Th=0.05 2oz 32mils anti-pad 40mils pitch Resistance increase with respect to the sheet resistance of solid plane Th=0.15 Th=0.2 6oz 8oz January 29 – 31, 2019

DC Effect in Perforated Planes Resistance vs. sheet thickness Th=0.05 Th=0.1 Zoomed resistance increase with respect to the sheet resistance of solid plane Th=0.2 Th=0.15 January 29 – 31, 2019

DC Effect in Perforated Planes Array of 9x9 antipads Parameterized array of antipads High conductivity port Sheet resistance increased values don’t change with respect to a single unit cell Single cell approach usable and scalable As the current goes into the middle, it’ll have the right current distribution January 29 – 31, 2019

0.7(28mils) antipad diameter, 0.2(8oz) copper thickness DC Effect in Perforated Planes Current density 0.7(28mils) antipad diameter, 0.2(8oz) copper thickness 90-degree wall 60-degree wall High Current density and power loss PORTS January 29 – 31, 2019

Server Simulation Voltage drop and Resistance 150Amps 10% difference in resistance. Just the power plane (on full board total dissipation 25W on all power-rails) Equivalent to rising the PCB temperature by 25C Pin groups equipotential making sims better 90 60 January 29 – 31, 2019

Summary and conclusions Etch factor for High Speed: First order effect is impedance (around 2 Ohms difference between rectangular and 90 degrees) Distant second is loss No much effect on vertical crosstalk through anti-pad opening Other: Be aware how and when to use unit cell approach, search for resonances Etch factor for DC (PI): With respect to vertical sidewalls, plane resistance will increase as the sidewall angle deviates from 90 degrees. With a 1-mm pitch and 28-mil anti-pad size the extra plane resistance through the perforated area increases by 8%, 18%, 29% and 44% for 50, 100, 150 and 200 um copper thicknesses, respectively. It’s not the same to have a single thick plane, that many small ones Via connections between planes will offset this conclusion. On a real server board the etch factor can account for up to 10% extra resistance and would be equivalent to a 25C rise January 29 – 31, 2019

THANK YOU! Any questions? January 29 – 31, 2019