Verilog-AMS Integration with P1800 SV Standard Srikanth Chandrasekaran Technical Chair, Verilog-AMS Committee

Verilog-AMS Standards Committee – Scope & Purpose The Verilog-AMS standards committee aims to address the needs of the mixed signal design community Enables top-down design methodology of AMS designs and allows designers to write early behavioral code of the mixed signal systems Provides capabilities and features to enable system level design and verification Standards committee comprises of team of experts in the AMS industry Volunteers comprise of both the developers (EDA tool developers) as well as consumers (design community) The Verilog-AMS committee has representation from about 10 companies that are either developing tools or mixed signal designs Ensuring interoperability Ensures any capability or enhancement done in the analog or the mixed signal part of the AMS language works with existing standards Interoperability is key: uniform implementation allows designs to be portable across tools

Industry Need for SV-AMS With P1364 being replaced with P1800, industry is adapting SystemVerilog for design as well as testbenches Enables top level design methodology & verification with SV testbenches Need to maintain the ability to simulate mixed signal designs Industry requires support for a mixed signal verification environment Vendors are already faced with the issue of how to support SystemVerilog along with existing mixed signal designs With Verilog-AMS being derived from 1364 Verilog, it is an obvious choice to enable the mixed signal modelling capabilities within SystemVerilog Need IEEE to address this critical issue In absence of a standard, vendors will go ahead with individual implementations Interoperability will become a very key issue Reconciling “vendor implementations” at later stage will become very difficult challenge.

AMS Activities beyond LRM2.3 Alignment with SystemVerilog (SV-AMS Integration Efforts) Having the unified BNF for Verilog-AMS with Verilog 1364-2005 as a subset means we already have some fundamental alignment with System Verilog Will allow the committee to take the next step and merge the analog and mixed signal constructs with the System Verilog language. Extending SV assertions to support Analog Verilog-AMS subcommittee is working on extensions to the current SVA language to support analog assertions This work would also require some requirements on the P1800 SystemVerilog language Verilog-AMS main committee working on enhancements and capabilities for mixed signal (mantis database) This effort will specifically look at the mixed signal items that have not been resolved in LRM2.3 Eg: multiple power domain support, other analog specific enahcements and minor fixes)

Options for SV-AMS Integration There are 3 possible options for integrating Verilog-AMS with SV Option 1: Deep integration of P1800 with Verilog-AMS LRM 2.3.1 Integration at the syntactic (BNF grammer) as well as semantic integration Need more commitment from P1800 committee to make this practical Option 2: Creating a P1800 “dot” standard Identified enhancements to the P1800 could be incorporated in separate dot standard Some fundamental enhancements might be proposed to the main P1800 committee A separate committee will be driving the dot standard efforts (with identified timelines etc) Need approval from P1800 main committee for any enhancements to SV?? Option 3: Merge subset of Verilog-AMS (without P1800 conflicts) with System Verilog Features that enable connectivity level mixing of Verilog-AMS and SV at the top level Initial first pass document generated on syntax difference between Verilog-AMS & P1800 2009 standard (an early P1800 draft version was used for this purpose) Document available at: http://www.eda-stds.org/verilog-ams/htmlpages/cdd.html