Federal University of Juiz de Fora The Use of Real-Time Simulation Technologies: Applications to electric Drive, Power Electronic and Grid Systems. Federal University of Juiz de Fora December 9, 2009 Christian Dufour, Ph.D. Senior Simulation Specialist, Power Systems and Drives Market Development Manager, Brazil

Lecture Plan Considerations About Real-Time Simulation Real-Time Simulators and Model-Based Design Hardware Components of a Real Time Simulator Solver Components of a Real Time Simulator Test Automation and Sequencer Using RT-LAB to Run Real Time Simulations Interesting Test Cases run on multi-core RT-LAB Conclusions

Considerations about real-time simulations

About the importance of simulation Let’s consider the design of an aircraft. Cost Billions$ to design and manufacture. Can we wait until the first flight test to verify it actually fly? Consider now a large power grid Again, it can cost $billions to design Can we wait until commissioning to make sure it is stable and robust?

Classic facility for power grid simulation Hydro-Quebec’s Network Simulation Center Motivation: Quebec power network is special: power generation is very far away from city. Many long lines. Requires a lot of active compensation. Focus: Real-time electrical network simulation. Needed to design new 765-kV line and specify the equipment (insulation co-ordination) using statistical technique Needed to test REAL controllers for an unstable network The real-network is not available (7 years to built) Cannot disconnect the real power grid for test purpose!!! Technical Challenges: High bandwidth, Large I/O count Complex model requiring massively-parallel hybrid computing Result: 20,000 sq. feet of hybrid simulator, 30 CPUs

Real-Time Simulation : Introduction Free Running Simulation Faster than real-time Slower than real-time

Real-Time Simulation : Introduction Sine equa none conditions for real-time algorithms Non-iterative Fixed –step (disqualify Spice-type or Saber simulation algorithm for example)

Main Purpose of Real-Time Simulation Actuators Sensors Main Purpose of Real-Time Simulation It is sometimes difficult to test a power systems device in its working environment or in real life condition. Solution: One can connect a real network device (ex: a FACTS controller) to a simulated power grid Other common applications: statistical testing, correlation testing MODEL OF POWER GRID

Evolution of Real-Time Simulator Technology RT-LAB 2009: 1 cabinet, 3 PC with 24 core in total For 350 3-ph buses 32 to 64 cores would be required to simulate the detailed HQ networks COTS Sim-On-Chip Hybrid (Analog/Digital) Simulators 1975 30000 square feet Hybrid Simulator Digital COTS Simulators Digital Custom Simulators Analog Simulators Model Based Design 1960 1970 1980 1990 2000

What is Model-Based Design? Model-Based Design is a methodology of design based on simulation models! Obviously! It is so common these days. Power grid designers were the first to use this approach philosophy, but 15 years ago and before, analog or hybrid simulator where used since computers were not fast enough But It was not always the case for other industries like automobile and power electronic: Before the advent of powerful computers and simulation tools, people used To write specifications on paper and use this to work with subcontractors Directly implement prototype on hardware Directly integrate modules into an analog test bench of simplified or complete system before integrating the real hardware and software

About the concept of Model-Based Design (simplified) Model Design (Simulink Block Diagram) Correct Design Iteratively Generate Software from Model Upload Software to RT Platform Test

Model Based Design (MBD) & Hardware-In-the-Loop (HIL) Models becomes the method to pass Information across teams Maintenance Design Validate Model  Off-line simulation Deployment Production Design & Implementation Virtual Prototype HIL, RT simulation 3D visualization Integration & Testing Integration & Test In-system commiss-ioning & calibration Control Prototype HIL, RT simulation, Physical Components Lab Testing with actual controller This implementation is made by the control team This implementation is made by the integration team Implementation Production Code Physical Components This implementation is made by the software team

Advantages of Model-Based Design Traditional Design Method Model Based Design Requirements Design & Build Release to Test Release to Field Combine to reduce weight, size and power Get crossed channels, blown circuits, failure propagation Debug early to reduce changes, minimize re-certification Advantages: Making Design Tradeoffs Early Reducing Development Cycle Reducing Testing Cost Better and More Tests Challenges: Requires expertise and effort Needs specialized tools Model fidelity Model management

Real-time simulation components Application Models Solvers Real-Time Platform Inputs/Outputs Communication Processing

Main components of a power system real-time simulator The 2 most critical components of a real-time power system simulators are: The hardware platform the capable to do these iteration fast enough Running a real-time Operating System With sufficient I/O capability Simulation solvers capable to iterate the equations of the power system with Accuracy Stability

Main components of a power system real-time simulator Other components Automatic test sequencer Because you want to run many tests automatically

Hardware component of real-time simulator

Hardware of a real-time power system simulator Two main approaches remains today Custom Digital Simulator ++ Optimized for power system problems -- Cost more, difficult to upgrade, less open, custom RTOS --- Not able to keep pace with new processing and communication technologies (3 to 5 years lagging behind the latest processors) Modern commercial-Off-The-Shelf Digital Simulator ++ Lower cost driven by mass market requirements: mainly the game industry that continuously requires faster CPUs, easy to upgrade ++ Flexibility: can connect any PCI card ++ Openness: Standard Operating system and can be easily interface to 3rd party software ++ Compatible with the latest processors very quickly as they become available.

RT-LAB eMEGAsim Simulator Hardware Architecture

RT-LAB eMEGAsim Simulator Hardware Architecture Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based CPU Sh.Mem. Simulink Model Multi-core Processors Shared-Memory Multi-CPU board HILBox PC1 PCI EXPRESS CPU Simulink Model Single-, Dual-, or Quad-Core PCI A commercially available standard computer motherboard, similar to what is used in high-end workstations or servers, is used as the main real-time computer unit. These computer boards, available from several manufacturers, have evolved from single processor Pentium II systems back in 1997 to dual quad-core 3.2 GHz processors, as of June 2009. As illustrated, a model can be divided across four subsystems and executed on a quad-core processors. The processor cores will then exchange their data through a very fast on-chip cache memory. Inter-processor communication can simply not be faster . Custom computers using old single-core processors and a local parallel commutation bus will communicate data at a much slower rate. A second quad-core computer can be added to simulate power systems with up to approximately 100 3-phase busses. This off-the shelf computer architecture enables point-to-point communication between each processor core . Each processor core of each processor chips can then communicate with each other through a very high-speed on-board shared-memory. This advanced technology is much faster that the old generation of custom computers using a slow parallel bus, shared by all processors, that enables communication between only two processors at a time. 20 20

RT-LAB eMEGAsim Simulator Hardware Architecture Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based CPU Sh.Mem. Simulink Model Multi-core Processors Shared-Memory Multi-CPU board HILBox PC1 PCI EXPRESS CPU Simulink Model Single-, Dual-, or Quad-Core PCI PCIe Extension User has the possibility to add PCI cards to the simulator with standard Protocol like TCP/IP, UDP/IP, RS-232 Or to develop and study its own protocols (IEC-61850, LoadRunner) PCI A commercially available standard computer motherboard, similar to what is used in high-end workstations or servers, is used as the main real-time computer unit. These computer boards, available from several manufacturers, have evolved from single processor Pentium II systems back in 1997 to dual quad-core 3.2 GHz processors, as of June 2009. As illustrated, a model can be divided across four subsystems and executed on a quad-core processors. The processor cores will then exchange their data through a very fast on-chip cache memory. Inter-processor communication can simply not be faster . Custom computers using old single-core processors and a local parallel commutation bus will communicate data at a much slower rate. A second quad-core computer can be added to simulate power systems with up to approximately 100 3-phase busses. This off-the shelf computer architecture enables point-to-point communication between each processor core . Each processor core of each processor chips can then communicate with each other through a very high-speed on-board shared-memory. This advanced technology is much faster that the old generation of custom computers using a slow parallel bus, shared by all processors, that enables communication between only two processors at a time. RS-232, CAN, TCP/IP IEC61850, LoadRunner 21 21

RT-LAB eMEGAsim Simulator Hardware Architecture Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based Multi-core processors Shared-Memory Multi-CPU board HILBox PC1 PCI EXPRESS CU FastCom CPU Sh.Mem. PCI Express Digital IO requirements For power electronic applications, the Digital I/O card is critical It must be capable of sampling Thyristor/ IGBT/GTO/MOSFET gate with great accuracy The latency must also be very low so it does not to slow down the simulation (PCI Express) 16 AO 16 AI Carrier w (op511x) 16 DO 16 DI Carrier (op5210) FPGA (op5142) The IO subsystem is managed in parallel by fast FPGA processors that take care of time critical IO synchronization using 10-nanosecond hardware timers. FPGA chips also manage data communication between the main processor memory and the FPGA memory using direct memory transfer (DMA), without disturbing the main processors. The main processor can then compute the model while the FPGA manages IO and the data transfer. Such a parallel technique contributes to reduced model time step and jitter. This is a key feature of OPAL-RT real-time simulators. The number of IO channels can easily be increased by adding IO and FPGA boards As described in the next slide, user models can also be executed directly on FPGA chips to achieve sub-microsecond time steps 22 22

Sampling of fast PWM gate signals For this purpose, PWM pulse are captured on the FPGA card by 100MHz counters Normalized ratio (Time stamp) is send to the inverter models on the CPU The model on the CPU use the Time Stamps to compute interpolated voltages

Effect of switch gate sampling and interpolation RTeDRIVE inverter model use the time stamps to produce very accurate results Example: a simple DC chopper (PWM=10kHz, Ts=10µs) Bad sampling (like if we use regular SPS) causes important non-linearity in the input-output characteristic But very linear caracteristic with RTeDrive TSB inverters SimPowerSystems TSB Tcarrier/Ts=10

Effect of switch gate sampling and interpolation Precise enough to take into account deadtime effect smaller that the sample Time Below is the effect of dead time increment of 2 µs (with a sample time of 10µs!)

Hardware Architecture (FPGA models) Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based Multi-core processors Shared-Memory, Multi-CPU board Xilinx System Generator Blockset Model HILBox PC1 PCI EXPRESS CU FastCom CPU Sh.Mem. PCI Express FPGA user programmability for advanced model design The FPGA card can be programmed by the user using Xilinx System Generator No VHDL language skill required. It is a Simulink blockset 16 AO 16 AI Carrier w (op511x) 16 DO 16 DI Carrier (op5210) FPGA (op5142) Xilinx SG model The IO subsystem is managed in parallel by fast FPGA processors that take care of time critical IO synchronization using 10-nanosecond hardware timers. FPGA chips also manage data communication between the main processor memory and the FPGA memory using direct memory transfer (DMA), without disturbing the main processors. The main processor can then compute the model while the FPGA manages IO and the data transfer. Such a parallel technique contributes to reduced model time step and jitter. This is a key feature of OPAL-RT real-time simulators. The number of IO channels can easily be increased by adding IO and FPGA boards As described in the next slide, user models can also be executed directly on FPGA chips to achieve sub-microsecond time steps Models with 10 ns sample rate can be coded on this card! 26 26

Simulator Hardware Architecture (Expandability) Host/Target Architecture Windows QNX & RT-Linux RTOS SIMULINK/RTW based Multi-core processors Shared-Memory Multi-CPU board HILBox PC1 PCI EXPRESS CU CPU Sh.Mem. HILBox PC2 Dolphin PCI Expandability FireWire INFINIBAND switch DOLPHIN SCI /PCIe (2 to 5 us latency) FPGA (op5142) 16 DO 16 DI Carrier (op5210) 16 AO 16 AI Carrier w (op511x) PCI Express 16 AO 16 AI Carrier w (op511x) 16 DO 16 DI Carrier (op5210) Power systems with up to 100 3-phase busses can easily be simulated at 50 microseconds with only one eMEGAsim module equipped with two quad-core processors running at 2.3 GHz.. The new i7 XEON 3.2 Ghz hyper-threading INTEL processors will enable the simulation of larger systems. These new high-performance processors will be tested in July 2009 as soon as they are available. This illustrates the advantage of using off-the shelf computers developed for the very competitive general computer market. We believe that this is much better than taking several months to develop new computer boards that will become obsolete as soon as they appear on the market! Larger power systems can be simulated by connecting additional eMEGAsim computer modules using 20-Gbit/s PCI Express communication adaptors and switches as illustrated on the next slide Dolphin 27 27

Solver components of real-time simulator

Simulation solvers for power systems Key characteristics of power systems Contains a wide range of frequency modes Requires ‘stiff’ fixed-step solvers. Stiff solver remains stable even with mode above the simulation Nyquist limit. Contains a lot of PWM-driven power electronics The simulator must avoid sampling effect when computing IGBT pulse ‘events’ internally or when reading PWM pulses from its I/Os

Stiff solvers methods for power system simulation Simulation methods electric systems: Nodal approach (EMTP, HYPERSIM) State-Space (SimPowerSystems, PLECS) Switching-function (inverter models only) FPGA-based methods

Stiff solvers methods for power system simulation Classic method ‘Nodal Approach’ Each RLC branch is discretized with the trapezoidal rule of integration (stiff solver) Example: inductor S-domain equation: Discretization by Trapeze( time step: T): Hummmm….. In depends on vn , a priori unknown nodal voltage Implicit problem, cannot iterate directly 

Stiff solvers methods for power system simulation ‘Nodal Approach’: solution to implicitness All branches resistance ratio R=vn/in , are build into a nodal matrix Known term Ih=in-1+(T/2L)vn-1 are built into a vector I For all nodes, a global matrix of admittance is built: YV=I Nodal voltages are found by solving this matrix problem, either by direct inversion or LU decomposition. Re-solving of Y required if a switch change position Y V= I 2 3 Ih -Ih R -R 4

Stiff solvers methods for power system simulation State-Space approach We can also find the exact state-space solution With k, matrix set index for switch permutations This can be discretized with the trapezoidal method like in SimPowerSystems for Simulink Trapezoidal method: order 2. It can also be discretized by higher order methods Higher order methods (order 5) implemented in ARTEMiS, a solver package of eMEGAsim.

Stiff solvers methods for power system simulation State-Space approach Continuous time state-space expression Solution for time step T: How to compute the ‘matrix exponential’ eAT ? Trapezoidal method (order 2) ARTEMiS art5 method (order 5) TALYOR EXPENSION

Effect of higher order discretization Simple case of RLC circuit energization Artemis ART5 solver more precise than Trapezoidal solver at 100 us

Numerical stability issues Discretized systems is not guarantied to be stable It depends on how Laplace poles are ‘mapped’ in the z domain. Ex: Forward Euler has poor stability A-stability (Stiff stability) (ex: trapeze method) guaranty discrete stability (for linear systems) Laplace pole (s) mapping RLC network Trapeze T=100µs Trapeze Stability Region -2/T Forward Euler Stability Region RLC network Euler T=0.01µs Im{l} y’=ly Re{l}

Numerical stability issues with trapezoidal integration Even if it is stable, the trapezoidal rule (tustin) is prone to numerical oscillations The z-domain mapping is stable but oscillatory for high frequency Laplace poles

Numerical stability issues with trapezoidal integration A-stable methods can be highly oscillatory How are mapped high frequency poles? It depends on the ‘stability function’ again X ARTEMiS art5 (L-stable) X Trapeze (A-stable) Laplace map Z- domain map Im{z} Im{l} y’=ly y(n+1)=zy(n) X Re{l} Re{z} -1 z mapping near -1 means oscillations

Switching function approach Other solver methods for power system simulation Switching function approach A special solver method for power electronic system using high-frequency PWM. It is a ‘simple’ controlled voltage source! Interpolation methods are used to obtain high accuracy in the Opal-RT RTeDRIVE package High impedance mode can be implemented now. V+ Gup Glow Load V_load ~V+ ~0 1 gate V_load * * V_load for positive I_load Gup Glow

Interpolated switching functions: example case 1 Mitsubishi Electric Co Japan, 2004 ARTEMiS used for rectifier side RTeDRIVE used for inverter © Opal-RT MITSUBISHI HIL Simulation Physical System PWM 9kHz 4.5kHz 2.25kHz 40

3-level STATCOM with 72 IGBT (Mitsubishi Electric) Interpolated switching functions: how high can you get? 3-level STATCOM with 72 IGBT (Mitsubishi Electric) 20 µs, 3 CPU with the controller 1000 time faster than conventional simulation software Actual diode/IGBT count: 10*6*3=180 Reference model In EMTP/RV (3us) vs Simulink/SPS/ RT-LAB (50 us) IPST 2009, Kyoto - Japan

Simulation On Chip (FPGA) RT-LAB XSG permits to use Xilinx System Generator models inside RT-LAB frame work Enables complex model to run on the FPGA of RT-LAB Examples: PMSM motor IGBT inverter, PWM modulator Power electronics

Simulation On Chip (FPGA) No need to know VHDL language But you need to know fixed-point arithmetic Stiffness problem is resolved because of the very small time step used (10 nanoseconds)! A typical XSG model in RT-LAB

Simulation On Chip (FPGA) Example: PMSM Drive Inverter and PMSM equation solved in FPGA Back-EMF stored in the FPGA also Inductance computed in CPU of the RT-LAB system at slower rate (40 µs) Torque is computed on CPU at 40 µs also. This is fine because it is used to compute mechanical equations anyway. *C. Dufour et al. “Real-Time Simulation of Finite-Element Analysis Permanent Magnet Synchronous Machine Drives on a FPGA card”, Proceedings of 2007 European Conference on Power Electronics and Applications (EPE-07) , Aalborg, Danemark , Sept 2007

Advanced solvers: State-Space Nodal (SSN) approach For all user-defined groups or subsystems. one state-space equation is found with some unknown entries, the NODAL voltage For all nodes , Thevenin/Norton equivalent are computed Then the unknown nodal voltage are found 45

Advanced solvers: State-Space Nodal (SSN) approach Advantages of the SSN approach Fewer state-space iterations Fewer switches per subsystems: precalculation is easier, which is important in RT-simulation Possibility to make parallel computation of the state-space groups in SSN Some similarities with MATE (J. Marti) GENE (K. Strunz) State-Space SSN

Update March 2010 Now released In ARTEMiS 6.0 Advanced solvers: State-Space Nodal (SSN) approach Small distribution system for breaker test coordination with: short pi line and 22 equivalent switches ADVANTAGES NO DELAY between subsystem solution Large number of switches allowed IN DEVELOPPEMENT Algorithm is tested in the the SPS environement using m-file S-function Currently ported to ‘C’ PERFECT MATCH WITH SPS Update March 2010 Now released In ARTEMiS 6.0 47

Advanced solvers: State-Space Nodal (SSN) approach Open question Is the SSN approach extendable to phasor-type (Transient Stability) simulation like MATE-type methods? 48

Comparison of solver methods Nodal State-Space (Real-Time case) SSN Switching function FPGA -Switch management is easier in RT application than SS. -Higher order solution possible: more precise High order solution. Switch mngt like nodal. Possible to optimize calculation with groups choices -Very Rapid -Very high number of switch can be handle - Very precise -Most Rapid - Basic Euler solver can be use because sample time is so low. -Order 2 method only - Risk of numerical oscillations when state dependence is present. -Possible memory problems in RT if too many coupled switches are present -Delay with the rest of the simulated (usually degligeable) - More difficult to implement because Fixed Point is less common Advantages Disadvantages

About the necessity for testing Test sequencer

Test sequencer: a key part of real-time simulator Test sequencer requirement Capability to launch test automatically Capability to record and analyze data Capability to manage models

Test sequencer: a key part of real-time simulator Usage case: controller correlation testing Today’s controllers are real piece of software Control algorithm may be less than 10% of the code 90% remaining: protections, diagnostics, user interface, etc… Each time the controller code is updated we need to verify its basic functionality are still working Done by automated tests With a digital plant, correlation is easy to determine Using random (Monte-Carlo) techniques to find worst cases

Test sequencer: a key part of real-time simulator Usage case: Monte-Carlo testing How to dimension correctly some power system component considering switching surges? ENTERGY POWER GRID 86 3-ph. busses 86 lines 23 loads 7-CPU simulation @ 50µs Bus B17 3-phase-fault

Test sequencer: a key part of real-time simulator By making automated randomized tests (Monte-Carlo), we can obtain probabilistic characteristics of overvoltages.

Test Automation with Python, ‘C’ or TestStand API of RT-LAB enable control by different software or methods

How to use RT-LAB for power system applications? 1- Design your model in Simulink and SimPowerSystems 2- Identify natural delay in your model (ex: transmission lines) 3- Make top-level groups in your Simulink model, these will be assigned to different CPUs of the simulator 4- Add I/O block in the model if necessary

How to use RT-LAB for power system applications? 1- Design your model in Simulink and SimPowerSystems We choose here a SPS demo named: power_PSS.mdl

How to use RT-LAB for power system applications? 2- Identify power line to make parallel distributed simulation

How to use RT-LAB for power system applications? 3- Choose a task separation and make Subsystems CPU #1 CPU #2

How to use RT-LAB for power system applications? 4- Some optimizations: put controllers in a separate CPU because it can run at slower rate Also put monitoring in a separate subsystem Controls Monitoring

How to use RT-LAB for power system applications? You can put your own ‘C’ code in any of the cores You just have to use a S-function ‘wrapper’ int main() { printf("hello, world"); printf(“I want to do real-time simulations"); return 0; }

How to use RT-LAB for power system applications? 5- Adding I/Os Let’s add an analog output from the RT-LAB library

How to use RT-LAB for power system applications? Let’s output the Alternator Excitation voltage

How to use RT-LAB for power system applications? The alternator excitation voltage can now be read on the front panel of the simulator

How to use RT-LAB for power system applications? Most commercial I/O cards can be supported Opal can supply the source code of communication driver examples to enable users to implement their own protocols through Ethernet for Internet Ex: Vestas proprietary protocol for wind farm communication, LoadRunner.

Other examples of power systems in real-time 86 3-ph. Busses 86 lines, 23 loads 7-CPU simulation @ 50µs

eMEGAsim 24-CPU 330-Bus power system # of bus 330 # of gen. 42(+1) # of load 90 # of DPL 517 New MILESTONE as of JUNE 2009

Example 3 – Industrial Motor Drives Multi Level Inverter Drive CONVERTEAM-ALSTOM (France) RT-LAB Electric Drive Simulator line voltage wave form 1200V This Controller is connected Externally to the Simulator

Example 3 – Industrial Motor Drives Multi Level Inverter Drive CONVERTEAM-ALSTOM (France) Pulse shutdown modeled with the help of Converteam Required the design of an hybrid switching-function with high-impedance capability Results of Hardware-In-the-Loop Tests Motor Acceleration Emergency Pulse shutdown

Example 4 – Wind-Turbines 10 Doubly-Fed induction machine with controllers (detailed models) Simulation controlled from RT-LAB TestDrive interface (Lab-View based)

Other examples (RT-simulation on 2-cores) 48-Pulse STATCOM compensated network (27 us) SVC system (15 us) Kundur system (18 us) 12 pulse HVDC system (15 us) All measures in shared-memory mode on Opteron Requirements for In-Transmission Control Modules

Large Power Grid with HVDC (7-core simulation @ 46µs) 6 buses 3 HVDC 3 plants Zone N: 10 buses 16 lines 2 plants 4 loads Zone E: 11 buses 20 lines 2 plants 4 loads Zone SW: 14 buses 23 lines 4 plants 7 loads

Key References University of Alberta Power Systems Laboratory based on RT-LAB L.-F. Pak, O. Faruque, X. Nie, V. Dinavahi, “A Versatile Cluster-Based Real-Time Digital Simulator for Power Engineering Research”, IEEE Transactions on Power Systems, Vol. 21, No. 2, pp. 455-465, May 2006. Hardware-In-The-Loop Testing of Motor Drive at Mitsubishi Electric Co. M. Harakawa, H. Yamasaki, T. Nagano, S. Abourida, C. Dufour and J. Bélanger, “Real-Time Simulation of a Complete PMSM Drive at 10 us Time Step”, Proceedings of the 2005 International Power Electronics Conference (IPEC 2005) – April 4-8, 2005 , Niigata, Japan. More about ARTEMiS solvers and power grid RT-simulation C. Dufour, S. Abourida, J. Bélanger,V. Lapointe, “InfiniBand-Based Real-Time Simulation of HVDC, STATCOM, and SVC Devices with Commercial-Off-The-Shelf PCs and FPGAs”, 32nd Annual Conference of the IEEE Industrial Electronics Society (IECON-06), Paris, France, Nov. 7-10, 2006 RT-LAB application booklet with over 30 applications explained from motor drives to large power systems. Requirements for In-Transmission Control Modules

Opal-RT Partial Customer List Opal-RT Technologies 2006.09.28

Opal-RT - Partial «Electrical» Customer List for Power Electronics in Hybrid Vehicles and Industrial Systems Rail Ford R&D

Thank you for your attention. See www. opal-rt Thank you for your attention! See www.opal-rt.com for more details or email me at: christian.dufour@opal-rt.com