Page Replacement Implementation Issues Text: Tanenbaum ch. 4.7

Instruction Backup Page handling involves restarting the instruction that causes the trap Need to determine the first byte of instruction - difficult for some CPUs CPU uses an internal hidden register to copy the PC before executing the instruction If page fault occurs here, where does the instruction begin?

Locking Page in Memory Virtual memory and I/O occasionally interact A process issues call for read from device into buffer while waiting for I/O, another process starts up has a page fault buffer for the first process may be paged out data from I/O may get loaded on the new page Need to specify some pages locked (pinning in memory) exempted from removal from memory

Backing Store (a) Paging to static swap area Proc size Proc size (a) Paging to static swap area - problem with process that increases in size after starting (b) Backing up pages dynamically - allocate disk space when the page is swapped out and deallocate it when it is swapped back in

Separation of Policy and Mechanism Where is the page replacement algorithm?

Growing Tables One dimensional address space with growing tables, one table may bump into another Consider a compiler table example:

Segmentation Divide the address space into segments and each segment can grow independent of each other segments have large address space to prevent bumping into each other two part address- a segment number and address within the segment

Advantages of Segmentation Modification and compilation of one segment’s procedure will not affect any other procedures in other segments (no starting address has been modified) Better sharing of procedures or data between processes (put shared libraries in a special segment) Different protection for different segments

8086 Memory Segmentation Details in https://www.scribd.com/document/326107534/Memory-Segmentation-of-8086 8086 has a 20-bit address bus (220 = 1MB) that can access 0x00000 to 0xFFFFF Supports 4 different segments (code, data, stack and extra) Segment registers are 16-bits wide (max size 64KB)

8086 Memory Segmentation Logical Address specified as: Based address: Offset Physical address = Append 0 to Base Adress + Offset For example: DS = 0x2222, Offset = 16 Local address = 0x2222: 0x16 Physical address = 0x22236

8086 Memory Segmentation (cont’d) Advantages: Allows the access of 1MB of memory with 16 bit registers Allows the placement of code and stack(or data) in different parts of memory Allows the placement in different areas of memory each time the program is executed (provision for relocation)

Comparison of Paging and Segmentation

Implementation of Pure Segmentation Segments are of various sizes (different from paging) Evicting and loading segments cause checker- boarding as in d) Need expensive memory compaction in e) to fill gaps

Segmentation and Paging To overcome the problem with pure segmentation, combine segmentation and paging. See reference in: http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media= onur-447-spring13-lecture18-virtual-memory-iii-afterlecture.pdf

x86 Segmentation with Paging x86 has 16K segments each holding 4GB of data To access a segment, x86 first loads a selector into one of CPU’s six segment registers (cs, ds, ss, es, fs, gs). The corresponding LDT or GDT is fetched and stored in microprogram registers. Requestor’s

Segment Descriptor Each program uses a Local Descriptor Table (LDT) to describe the code, data, stack etc. A single Global Descriptor Table(GDT) shared among all programs describes OS etc. Code segment descriptor:

Details about GDT From https://staktrace.com/nuggets/index.php?id=11&replyTo=0 Bits 63-56: Bits 31-24 of the base address  Bit 55: Granularity bit (set means the limit gets multiplied by 4K)  Bit 54: 16/32-bit segment (0=16-bit, 1=32-bit)  Bit 53: Reserved, should be zero  Bit 52: Reserved for OS  Bits 51-48: Bits 19-16 of the segment limit  Bit 47: The segment is present in memory (used for virtual memory stuff)  Bits 46-45: Descriptor privilege level (0=highest, 3=lowest)  Bit 44: Descriptor bit (0=system descriptor, 1=code/data descriptor)  Bits 43-41: The descriptor type (see below for an enumeration of the types)  Bit 40: Accessed bit (again, for use with virtual memory)  Bits 39-16: Bits 23-0 of the base address  Bits 15-0: Bits 15-0 of the segment limit  The type of the segment is stored in bits 43-41, and has one of the following values:  Bit 43: executable (0=data segment, 1=code segment)  Bit 42: expansion direction (for data segments), conforming (for code segments)  Bit 41: read/write (for data segments: 0=RO, 1=RW) (for code segments: 0=Execute only, 1=Read/execute) 

Conversion to Linear Address Segment translation- logical address (what the applications see) to linear address (address for each segment) Page translation- linear address to physical address Logical(Virtual) Address 16-bit 32-bit Local/Global

Mapping of a linear address onto a physical address

Protection on x86 Both Linux and Win32, only 0 and 3 are used Access to segments done by evaluating: CPL: internal register stores current privilege level DPL: descriptor privilege level RPL: requestor’s privilege level Level