1. Memory Management Paging (continued) Segmentation
CS350 & CS552

2. Implementation Issues in Paging
Four times when OS involved with paging
Process creation
determine program’s resident-set size
create page table
Process execution
MMU reset for new process
TLB flushed
Page fault time
determine virtual address causing fault
swap target page out, needed page in
Process termination time
release page table, pages
CS552

3. Page Fault Handling (1) Hardware traps to kernel, t1 is interrupted
Context switch into kernel: Privilege mode ON, Interrupts OFF, Protection OFF
General (users) registers saved
OS determines which virtual page needed
OS checks validity of virtual address
OS Seeks target/victim; if victim dirty, then write it to disk
OS schedules I/O request for new page from disk
OS dispatches another task (tn), while waiting
Page-in I/O completes, t2 registers saved
Page tables updated
Faulting instruction backed up to when it began
Faulting process scheduled
Registers restored
Program (t1) continues
CS552

4. Locking Pages in Memory
Virtual memory and I/O occasionally interact
Proc issues call for read from device into buffer
while waiting for I/O, another processes starts up
has a page fault
buffer for the first proc may be chosen to be paged out
Need to specify some pages locked
exempted from being target pages
CS552

5. Separation of Policy and Mechanism
Page fault handling with an external pager
CS552

6. Segmentation (Pt1) One-dimensional address space with growing tables
One table may bump into another (solution?)
CS552

7. Allows each table to grow or shrink, independently
Segmentation (Pt2)
Allows each table to grow or shrink, independently
CS552

8. Comparison of paging and segmentation
Segmentation (Pt3)
Comparison of paging and segmentation
CS552

9. Implementation of Pure Segmentation
(a)-(d) Development of checkerboarding (external fragmentation)
(e) Removal of the checkerboarding by compaction
CS552

10. Segmentation with Paging: MULTICS (Pt1)
Segment descriptor – numbers are field lengths
Descriptor segment points to page tables
CS552

11. Segmentation with Paging: MULTICS (Pt2)
Conversion of a 2-part MULTICS address into a main memory address
CS552

12. Segmentation with Paging: Pentium (Pt1)
Similar to MULTICS, but addresses a number of different design goals
A Pentium selector
GDT = Global Descriptor Table
LDT = Local Descriptor Table
Code segment descriptor
Data segments differ slightly
CS552

13. Segmentation with Paging: Pentium (Pt2)
Conversion of a (selector, offset) pair to a linear address
CS552

14. Segmentation with Paging: Pentium (Pt3)
Mapping of a linear address onto a physical address
CS552

15. Segmentation with Paging: Pentium (Pt4)
Level
Protection on the Pentium
CS552

16. References Chapters 8 and 9 :OS Concepts, Silberschatz, Galvin, Gagne
Chapter 4: Modern Operating Systems, Andrew S. Tanenbaum
X86 architecture
Memory segment
Memory model
IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture
CS552