Synplify Global Clock Resource Attributes 3/31/2017 8:39 PM Synplify Global Clock Resource Attributes December 2013 Tecnomic Bangalore © 2007 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries. The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

Global Resource s Proasic3 Devices has 6 Global Resources available 3/31/2017 8:39 PM Global Resource s Proasic3 Devices has 6 Global Resources available Synplify Will promote the signals based on the fan-out of the signal Different signal has different fan-out threshold for global promotion Clock nets—2 Asynchronous set/reset—12 Data nets—5000 You can change the threshold in the Synplify settings © 2007 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries. The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

Controlling the Global Promotions 3/31/2017 8:39 PM Controlling the Global Promotions Types of Control is available Enable Only Specific signal to be promoted Disable Only Specific Signal from Promoted Disable All Global Promotion © 2007 Microsoft Corporation. All rights reserved. Microsoft, Windows, Windows Vista and other product names are or may be registered trademarks and/or trademarks in the U.S. and/or other countries. The information herein is for informational purposes only and represents the current view of Microsoft Corporation as of the date of this presentation. Because Microsoft must respond to changing market conditions, it should not be interpreted to be a commitment on the part of Microsoft, and Microsoft cannot guarantee the accuracy of any information provided after the date of this presentation. MICROSOFT MAKES NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, AS TO THE INFORMATION IN THIS PRESENTATION.

Enable Only Specific Signals syn_insert_buffer attribute This method will allow a specific signal to be promoted to the global resource This can override the default fan-out guide as well The below example will promote Port CLK to a global resource define_attribute {clk} {syn_insert_buffer} {CLKBUF}

Disable Only Specific Signals syn_noclockbuf attribute This method will disbale the specific signal from promoted to the global resource The below example will disable Aclr port from using the Global resource define_attribute {aclr} {syn_noclockbuf} {1}

Disable All Global Promotion syn_noclockbuf ( define_global ) attribute Use the syn_noclockbuf attribute with the global reach to achieve the same All the signals will be buffered using regular buffer Specific signal can be promoted to the Global using the other attribute define_global_attribute syn_noclockbuf {1}

Example Design: No Constraints Synplify Report Synplify log file First Synthesis the Design to Find the High Fan-out Nets Look under the High Fan-out nets section in synplify log file Following signal are promoted to global “aclr” -- aclr_c “clk” -- clk_c “enable” -- enable_c “clk2” -- un2_clk2 High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------- un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 =============================================================== @N:FP130 : | Promoting Net aclr_c on CLKBUF aclr_pad @N:FP130 : | Promoting Net enable_c on CLKINT I_141 @N:FP130 : | Promoting Net clk_c on CLKBUF clk_pad @N:FP130 : | Promoting Net un2_clk2 on CLKINT I_142 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication

Example Design: Create new constraints File Counter.sdc Create a new “sdc” file in Libero Use the syn_noclockbuf attibute Add to synthesis project when invoking synplify from libero ## counter.sdc ## Disable Global Buffer Promotion for Entire design, ## No Global Buffer will be used by Default define_global_attribute syn_noclockbuf {1}

Example Design: Disable All Global Synplify Log file No Global Buffer used All the 4 Signals are buffered using regular Buffers Some Signals will be replicated 6 regular buffers used in this design ( 0 buffers without the attibute High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------- un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ========================================================== Buffering enable_c, fanout 142 segments 3 Buffering clk_c, fanout 87 segments 2 Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 6 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication

Example Design: Promote Only Specific Signal to Global This time “clk” signal being promoted to Global All other signals remains same Signal CLK is missing from the buffer tree this time counter.sdc define_global_attribute syn_noclockbuf {1} define_attribute {clk} {syn_insert_buffer} {CLKBUF} Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes --------------------------------------------------------------- un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ================================================== Buffering enable_c, fanout 142 segments 3 Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 5 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication Synplify log file ###########################################################] Premap Report Adding property syn_noclockbuf, value 1 to view:work.counter(one)

Example Design: Disable only Specific Signal restrict “aclr” from being promoted to global All other signal can be promoted to global depending on the fan-out Note that the global restriction constraint is commented(#) and not used Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name     Fanout, notes                    --------------------------------------------------------------- un2_clk2 / Y                   71                               aclr_pad / Y                   158 : 158 asynchronous set/reset enable_pad / Y                 142                              =============================================================== @N:FP130 :  | Promoting Net enable_c on CLKINT  I_141   @N:FP130 :  | Promoting Net clk_c on CLKBUF  clk_pad   @N:FP130 :  | Promoting Net un2_clk2 on CLKINT  I_142   Buffering aclr_c, fanout 158 segments 4 Added 3 Buffers Added 0 Cells via replication     Added 0 Sequential Cells via replication     Added 0 Combinational Cells via replication counter.sdc #define_global_attribute syn_noclockbuf {1} # Disable Global Buffer Promotion for aclr Signal define_attribute {aclr} {syn_noclockbuf} {1}

Example Design: Restrict Internal Signal from promoting Counter.vhd “.sdc” file method may not work for internal signal Use the attribute in hdl file Example shows restricting “clk2” disabled from promoting High Fanout Net Report ********************** Driver Instance / Pin Name     Fanout, notes                    --------------------------------------------------------------- un2_clk2 / Y                   71                               aclr_pad / Y                   158 : 158 asynchronous set/reset enable_pad / Y                 142                              =============================================================== @N:FP130 :  | Promoting Net enable_c on CLKINT  I_141   @N:FP130 :  | Promoting Net clk_c on CLKBUF  clk_pad   Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 3 Buffers Added 1 Cells via replication     Added 0 Sequential Cells via replication     Added 1 Combinational Cells via replication Counter.vhd signal qaux2 : std_logic_vector(15 downto 0); signal clk2 : std_logic; attribute syn_noclockbuf : boolean; attribute syn_noclockbuf of clk2 : signal is true; begin

Example Design: Promote Internal Signal to global Counter.sdc “.sdc” file method may not work for internal signal Use the attribute in hdl file Example shows promoting “clk2” to global All other signals are restricted using the global constraint in sdc file ## All signals are barred from being promoted to global define_global_attribute syn_noclockbuf {1} Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name     Fanout, notes                    --------------------------------------------------------------- un2_clk2 / Y                   71                               aclr_pad / Y                   158 : 158 asynchronous set/reset enable_pad / Y                 142                              ========================================================== @N:FP130 :  | Promoting Net clk2 on CLKINT  clk2   Buffering enable_c, fanout 142 segments 3 Buffering clk_c, fanout 87 segments 2 Buffering aclr_c, fanout 158 segments 4 Added 6 Buffers Added 0 Cells via replication     Added 0 Sequential Cells via replication     Added 0 Combinational Cells via replication Counter.vhd signal qaux2 : std_logic_vector(15 downto 0); signal clk2 : std_logic; attribute syn_insert_buffer : string; attribute syn_insert_buffer of clk2 : signal is "CLKINT"; begin