Interconnect with Cache Coherency Manager

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Presentation transcript:

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 I 100 00 10 B0 S 108 00 08 B1 S 108 00 08 B1 M 128 20 10 B2 M 110 00 10 B2 I 130 10 12 B3 I I 118 00 18 B3 120 10 28 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 Initial State 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 10 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 10 B2 M 110 00 10 B2 I 130 10 12 B3 I I 118 00 18 B3 120 10 28 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 1: P0: read 128 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 10 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 10 B2 M 110 00 10 B2 I 130 10 12 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 2: P1: read 132 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 M 128 20 15 B0 S 108 00 08 B1 S 108 00 08 B1 I 128 20 10 B2 M 110 00 10 B2 I 130 10 12 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 3: P0: write 128  20 15 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 15 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 15 B2 M 110 00 10 B2 I 130 10 12 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 4: P1: read 128 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 15 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 15 B2 M 110 00 10 B2 I 130 10 12 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 5: P0: reads 110 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 15 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 15 B2 S 110 00 10 B2 S 110 00 10 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 After reference 6: P1: reads 110 108 00 08 110 00 10 118 00 18 120 10 28 128 20 10 130 10 12 132 40 12 134 10 22

Interconnect with Cache Coherency Manager Processor 0 Processor 1 Block State Tag Data Block State Tag Data B0 S 128 20 15 B0 S 108 00 08 B1 S 108 00 08 B1 S 128 20 15 B2 S 110 00 10 B2 S 110 00 10 B3 S 132 40 12 B3 S 132 40 12 Interconnect with Cache Coherency Manager Tag Block Data Memory 100 00 10 Memory after cache write-back: 108 00 08 110 00 10 118 00 18 120 10 28 128 20 15 130 10 12 132 40 12 134 10 22