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How caches take advantage of Temporal locality
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How caches take advantage of Spatial locality
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Cache Hits
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Cache Misses
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Cache Design
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Mapping schemes Direct Mapped Set Associative Fully Associative
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Direct Mapped Each main memory address maps to exactly one cache block Here is 16-byte main memory and a 4-byte cache (four 1-byte blocks) Memory locations 0, 4, 8 and 12 map to cache block 0 1, 5, 9 and 13 to cache block 1
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How to map a memory address
One way to use the mod operator (reminder) If a cache contains 2k blocks, then data at memory address i would go to cache block index i mod 2k address 14 maps to cache block 2 14 mod 4 = 2
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How to map a memory address
Another way is to look at the least significant k bits of the address With 4-byte cache we would inspect the two least significant bits of our memory addresses So address 14 (1110) maps to cache block 2(10)
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How to map a memory address
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How to find data in the cache
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Solution
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Tag + Index
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The valid bit
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Cache hit
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Loading a block into the Cache
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Spatial Locality
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Block Addresses
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Cache mapping
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Example Given a cache with 1024 blocks of 4 bytes each, and 32-bit memory addresses, then where would the byte of memory address 6147 be stored? 6147 = Tag Index block offset Block address in M.M = 1536 Block # 512 in the cache third byte Solution 1 11
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Example Given a cache with 1024 blocks of 4 bytes each, and 32-bit memory addresses, then where would the byte of memory address 6147 be stored? Block address in M.M = / 4 = Index = 1536 mod 1024 = 512 Block offset = 6147 mod 4 = 3 Solution 2
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Cache Performance If a program uses addresses 2, 6, 2, 6,2,6, …., then each access will result in a cache miss
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Cache Performance
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Direct Mapped Cache: Example Ram=128 add
Tag Byte offset Index Byte address Miss: valid load load load Miss: tag Miss: tag Miss: valid Miss: tag 5/5 Misses Index Valid Tag Data 00 N 01 10 11 Y 000 Memory[ ] Y 010 Memory[ ] Y 000 Memory[ ] Y 010 Memory[ ] Y 001 Memory[ ]
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2-Way Set Associative Cache: Example
load Byte offset Tag Index Byte address Miss: valid load 0 load Miss: tag load 32 load Hit! load 0 load Miss: tag load 24 load Miss: tag load 32 4/5 Misses Index Valid Tag Data N 1 Y 00000 Memory[ ] Y 0100 Memory[ ] Y 0100 Memory[ ] Y 0011 Memory[ ]
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Fully Associative Cache: Example
load Byte offset Tag Index Byte address Miss: valid load 0 load Miss load 32 load Hit! load 0 load Miss load 24 load Hit! load 32 3/5 Misses Valid Tag Data N Y 0000 Memory[ ] Y 0100 Memory[ ] Y 0110 Memory[ ]
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Performance of Memory System
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