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Computer System Design Lecture 9

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Presentation on theme: "Computer System Design Lecture 9"— Presentation transcript:

1 241-440 Computer System Design Lecture 9
Wannarat Suntiamorntut W.S.

2 Memory Technology W.S.

3 Technology Trend Capacity Speed Logic : 2x in 3 years 2x in 3 years
DRAM : 4x in 3 years 2x in 10 years Disk : 4x in 3 years 2x in 10 years W.S.

4 Processor-DRAM memory Gap
W.S.

5 Expanded of Memory System
W.S.

6 Hierarchy of Modern computer
W.S.

7 How hierarchy manage? Registers <--> Memory by compiler
Cache <--> Memory by Hardware Memory <--> Disks by Hardware/OS, programmer (files) W.S.

8 Logic Diagram of a Typical SRAM
W.S.

9 Typical of SRAM Timing W.S.

10 Classical DRAM Organization
W.S.

11 Logic Diagram of a Typical DRAM
W.S.

12 Art of Memory Design W.S.

13 1 KB Direct Mapped Cache with 32 B Blocks
W.S.

14 Example : Fully Associative
W.S.

15 A Two-way Set Associative Cache
W.S.

16 Disadvantage of Set Associative Cache
W.S.

17 How do you Design Cache? W.S.

18 1 KB Direct mapped Cache, 32B blocks
W.S.

19 Improvement of Cache Reduce Miss rate Reduce Miss penalty
Reduce time to hit in cache W.S.

20 Where can a block be placed in the upper level?
W.S.

21 Example W.S.

22 Next on Lecture 10 W.S.


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