An Efficient Tile-Based ECO Router with Routing Graph Reduction and Enhanced Global Routing Flow Jin-Yih Li Yih-Lang Li Computer & Information TSMC Science Department, National Chiao-Tung University (NCTU) 2018/11/28

New ECO Routing Design Flow Outline Introduction New ECO Routing Design Flow Experimental Results Conclusion Introduction 2018/11/28

ECO Routing ECO routing is commonly requested toward the end of the design process to optimize delay and noise or to complete an imperfect layout. ECO routing is highly complicated many existing interconnections different design rules for delay and noise issues Most of ECO routing can be solved by p2p routing. 2018/11/28

The Design Flow of Tile-Based Router Routing Flow Corner-Stitching Tile Plane Construction Tile Propagation Path Construction 8 tiles 2018/11/28

Tile Propagation C10 T C11 C9 C7 C8 C6 C5 C4 C3 S C1 C2 2018/11/28

Path Construction Path Construction generates a minimum-corner path that passes through the list of visited tiles. * * 2018/11/28

Routing Example Contour Insertion 2018/11/28

Routing Example Corner Stitching Tile Plane Creation 2018/11/28

Routing Example Tile Propagation 2018/11/28

Routing Example Path construction 2018/11/28

Challenges for Tile-based ECO Routing Tile fragmentation – too many slim tiles Reducing the no. of tiles can promote router speed A horizontal-layer tile plane without contour insertion A horizontal-layer tile plane after contour insertion 2018/11/28

Contributions of This Work We propose routing graph reduction to reduce tile fragmentation so that the ECO router can run twice as fast without sacrificing routing quality. We propose a newly enhanced global routing flow to reduce the runtime of ECO routing by around 89% 2018/11/28

New ECO Routing Design Flow Introduction New ECO Routing Design Flow Experimental Results Conclusions New ECO Routing Design Flow 2018/11/28

New ECO Routing Design Flow Build corner-stitching tile planes Redundant Tiles Removal Routing Graph Reduction Neighboring Tiles Alignment Global Routing GCell Restructuring Fail No Feasible Solution Tile Propagation ExtendedRouting Success Feasible Solution Found Enhanced Global Routing Flow Path Construction 2018/11/28

Redundant Tiles Removal Definition conjunct tile. A tile A is referred to a conjunct tile of a tile B if the tile propagation from A to B on the same layer or across adjacent layer is feasible. Definition 1-conjunct. A space tile is said to be one-conjunct if it has only one conjunct tile. Definition 0-conjunct. A space tile is said to be 0-conjunct if it has no conjunct tile. 2018/11/28

Redundant Tiles Removal The 1-conjunct space tile is redundant because those paths that enter a 1-conjunct space tile have no exit. The 0-conjunct space tile is redundant because it can not be reached from any other space tile. We remove these redundant tiles within an enumeration over the whole tile plane. 2018/11/28

Redundant Tiles Removal T1(1-conjunct) T2(0-conjunct) T3(1-conjunct) Block Tile Space Tile Via region ( the region that can accommodate new via) Block Tile : 10 Space Tile: 16 2018/11/28

Redundant Tiles Removal Block Tile : 10  6 Space Tile: 16  13 26  19 2018/11/28

Neighboring Tiles Alignment We can adjust and align the left and right sides of two adjacent block tiles to merge them as a block tile. Adjusting border is to enlarge block tiles and to shrink space tiles. Cut lines 2018/11/28

Neighboring Tiles Alignment (T1,T2) T1 T5 T3 (T3,T4) T2 T4 T6 (T5,T6) 2018/11/28

Four Shrinking Cases All these four cases are trying to merge block tiles T2 and T3 Ta active tile (the tile under process) (1) (2) T1 T2 T1 T2 Ta T3 Ta T3 (3) (4) T2 Ta T2 Ta T3 T1 T3 T1 2018/11/28

Shrinking Rule Case 1 T2 T1 T1 Ta Ta (a) illegal (b) illegal Stop position Start position Stop position Start position (a) illegal (b) illegal Shrinking rule:  There exists no via region overlapping with the shrinking region.  The shrunk tile has no top or bottom neighboring space tile whose left border is larger than or equal to the stop position and less than the start position. 2018/11/28

Shrinking Example T2 Shrunk tile Ta Block Tile : 5 Space Tile: 11 2018/11/28

Shrinking Example T2  10 Block Tile : 5 Space Tile: 11 Total 16  10 2018/11/28

Enhanced Global Routing Flow Build corner-stitching tile planes Redundant Tiles Removal Routing Graph Reduction Neighbor Tiles Alignment Global Routing GCell Restructuring Fail No Feasible Solution Tile Propagation ExtendedRouting Success Feasible Solution Found Enhanced Global Routing Flow Path Construction 2018/11/28

Partition Layout into GCell 2018/11/28

Create Global Routing Graph 2018/11/28

Internal Edge of A GCell B nw en nw en ew ew ns ns ws ws se se C D nw en nw en ew ew ns ns ws ws se se 2018/11/28

Cost Function For each vertex v in G, we define a cost c VC = VA/A VC: Via capacity of a GCell VA: The total via region of a GCell A : The area of a GCell For each edge e in G, we define a length cost lc = 2/t. 1/VC if VC＞ t c = k/VC if VC≦ t t: threshold value for a routable area k: amplification scalar It’s hard to pass through a Gcell when VC < 0.01 2018/11/28

Find Minimum-Cost Path GCell on minimum cost path : Active GCell Other: idle GCell s t 2018/11/28

Idle Path Heap IPH GCell B (active) GCell A (idle) T1 T3 T2 2018/11/28

Blocked GCell s t E A B C D 2018/11/28

Extended Routing s t E A B C D Pop up cells D and E’s idle path heaps and continue tile propagation s t E A B C D 2018/11/28

Successful Extending Routing 2018/11/28

GCell Restructuring GCell restructuring is performed if extended routing fails. E B C A E D nw en A C B ew ns ws se D C & E’s idle path heaps are empty, so we disconnect internal edges nw and ew 2018/11/28

GCell Rescheduling s t D F G 2018/11/28

GCell Rescheduling s t D I H F G 2018/11/28

New ECO Routing Design Flow Introduction New ECO Routing Design Flow Experimental Results Conclusions Experimental Results 2018/11/28

Tile Plane Construction (Tcs) Experimental Results Table 1. Statistics of the design under test # of Standard Cell # of M2 rect. # of M3 rect. # of via1 rect. # of via2 rect. 114,155 632,634 399,993 399,852 618,218 Table 2. The number of tiles on the corner stitching tile planes Layer Origin After RGR #Block Tiles #Space Tiles # Block Tiles Met2 1067,179 973,528 470,325 380,798 Met3 591,120 541,706 289,144 218,444 Total 3,173,533 (C1) 1,358,711 (C2) Reduction rate 0.571 ( (C1-C2)/C1) Table 3. The pre-process time before routing Pre-process Tile Plane Construction (Tcs) RGR (Trgr) Time (second) 21.656 5.889 ※ RGR: Routing Graph Reduction 2018/11/28

Experimental Results  ½ Table 4. Routing results with applying Routing Graph Reduction Test name Pure tile-based router Apply RGR T1(%) T2(%) RT (Ta) WL (Wa) #Vias (Va) (Tb) (Wb) (Vb) TEST1 128.3 12035.07 480 65.8 12035.08 48.7   44.2 TEST2 82.6 11553.93 478 41.8 11553.96 49.5 42.3 TEST3 73.9 11399.45 394 38.3 11399.48 48.2  39.4 TEST4 65.3 9667.94 398 33.1 9667.97 49.3  40.3 TEST5 52.2 11194.86 508 26.5 11194.92 49.7 38.0 TEST6 121.5 12618.18 498 64.4 12618.21 47.0 42.2 TEST7 147.1 11732.99 502 75.6 11733.03 48.7 44.7 average 41.6  ½ ※T1 : (Ta-Tb)/Ta, T2 : (Ta-(Tb+Trgr))/Ta ※RT : routing time(second), WL: wire length(um) 2018/11/28

Experimental Results Table 5. Routing results with applying Enhanced Global Routing Test name Pure tile-based router Apply Enhanced Global Routing T3 (%) W V RT (Ta) WL (Wa) #Vias (Va) (Tc) (Wc) (Vc) #ER #GCRS TEST1 128.3 12035.07 480 14.7 12497.55 184 88.6 3.8 -61.6 TEST2 82.6 11553.93 478 8.3 12607.58 530 1 89.9 9.1 10.8 TEST3 73.9 11399.45 394 7.2 12173.36 536 90.4 6.7 36.0 TEST4 65.3 9667.94 398 8.8 10687.03 416 4 86.5 10.5 4.5 TEST5 52.2 11194.86 508 9.3 14437.81 588 2 82.4 28.9 15.7 TEST6 121.5 12618.18 498 9.8 13533.45 516 92 3.6 TEST7 147.1 11732.99 502 11.3 13097.15 262 92.3 11.6 -47.8 average 88.9 11.1 ※ T3 : (Ta-Tc)/Ta, W : (Wc-Wa)/Wa, V: (Vc-Va)/Va ※ ER : Extended Routing, GCRS: GCell restructuring and rescheduling 2018/11/28

New ECO Routing Design Flow Introduction New ECO Routing Design Flow Experimental Results Conclusions Conclusions 2018/11/28

Conclusions We propose a new ECO routing design flow to promote router speed. routing graph reduction can reduce tile fragmentation so that tile propagation speed can be doubled. With the enhanced global routing flow, ECO router can perform much faster at the cost of a small decline in routing quality. 2018/11/28

THANK YOU VERY MUCH 2018/11/28