ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #14 Agenda Today Resets and Clock System Computer-Operating-Properly Watchdog MSP430 Timer_A Module Timer_A Example: Timer Overflow Interrupt Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Resets Power-On Reset (POR) Caused by hardware. Response of hardware to brownout (low-power) condition. Hard power-on is extreme case of brownout. Can happen if physical RST pin is asserted. Some MSP430s have a Supply Voltage Supervisor (SVS) that can generate a power-on condition if supply voltage drops below acceptable levels. Power-Up Clear (PUC) Distinctive from power-on reset. Caused by software conditions. Watchdog timer expiration. Software-generated reset condition (bad Watchdog password). Runaway Flash memory programming (bad Flash controller password). Access violations (reading IC from peripheral registers…) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Resets Conditions after reset Initial conditions for registers and peripherals vary (see datasheet for details). General effects: RST/NMI pin configured as RST. Most input/output pins configured as inputs: Software should configure unused pins as outputs (or otherwise ensure unused inputs are not floating). Peripheral registers set the way the datasheet says: rw-0 notation means: readable/writeable and initialized to 0 on PUC. rw-(0) notation means: readable/writeable and initialized to 0 only on POR. Status register is cleared (brought out of low-power mode if necessary). Watchdog timer is enabled: Software should explicitly disable if not used. Program counter (R0) is loaded with the reset vector. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Resets What caused the reset? Can be determined through the IFG1 and perhaps other flag registers. The following bits will be set to identify the source of the reset: WDTIFG: Watchdog caused reset. OFIFG: Oscillator fault (non-maskable interrupt actually, not a reset). RSTIFG: RST pin was asserted. PORIFG: Set on power-on reset (POR). NMIIFG: NMI pin was asserted (non-maskable interrupt actually, not a reset). On PUC: The WDTIFG bit is not cleared—so the source of the PUC can be determined. Other flags for Flash security and the supply voltage supervisor (if applicable) exist elsewhere (see datasheets). Doesn’t appear to be a flag for an illegal opcode! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Resets A Few Hardware Considerations Be careful with RST pin! Should never be left floating and de-coupled from noise as best as possible. Modern uCs/uPs can have very sensitive RST lines! Poor quality power supplies can cause problems. A slow supply power rise on power up (for example) can cause problems (hardware software race condition). Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Clock System Multiple Clock Domains for CPU and Peripherals Multiple clock domains are provided because perhaps the CPU doesn’t need to run as fast as the peripherals—or vice versa. Clocking faster than necessary wastes power without end-user benefit!  Should run CPU and peripherals no faster than necessary to give desired functionality. Clock domains in MSP430: Master Clock (MCLK)  CPU is driven by this Sub-System Master Clock (SMCLK) Auxiliary Clock (ACLK) Different peripherals may use different clock domains. Each of the three clock domains above can be sourced by different oscillator sources (see section 5.8 of text book or datasheet). Each of the three clock domains can also be divided down by a factor of 1, 2, 4, or 8. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Clock System Defaults The CPU (MCLK) is driven by a digitally controlled oscillator (DCO) at a frequency of about 1 MHz. The sub-system master clock (SMCLK) is also driven by DCO at ~1 MHz. ACLK comes from a low-frequency, external oscillator if present. Clock Module Control DCOCTL and BCSCTL1-3 registers. Flags in IFG1 and IE2 for reporting faults with oscillators. Some clock signals can be brought out of the uC through port pins (configured as outputs) for use by external devices. External crystals can be more accurate than an RC-based internal oscillator—but usually this accuracy is not required. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Clock System Do clock accuracy and stability matter? Accuracy: How close the frequency is to the advertised. Stability: How much or little the frequency shifts with time and temperature. How long will your system run without a reset? Is precise timing needed? Are you keeping track of “real time”? What range of temperatures will your system be operating in? … Status Register Control of Clock Module Remember that 4 bits in the SR enable and disable parts of the clock module to facilitate low-power modes! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Clock System Oscillator Faults Having multiple oscillator candidates for a clock source allows for some fault tolerance! What happens if an external crystal oscillator fails and your system is part of a satellite in space?  Software can switch over to an alternate, less-desirable or backup oscillator as a fail-safe! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Detecting Oscillator Faults An RC circuit can be used as a primitive way of detecting an oscillator fault. (The MSP430 likely uses a more sophisticated hardware technique) Remember:  = RC Vout = Vin · e-(t/) Volts (V) Time (t) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Interrupt Overhead (Latency) Interrupts take a fixed number of clock cycles to initialize and get ready to execute the ISR. The MSP430 takes 6 cycles to enter an ISR. The RETI instruction takes another 5 cycles to return to the interrupted code. Instructions that have started execution cannot be interrupted. If an instruction had just begun execution and an interrupt occurs, the instruction must complete—and then the 6-cycle overhead begins. The longest instruction in the MSP430 takes 6 cycles. So worst case, it may take 12 cycles to get into an ISR. The overhead should be measured to determine if an interrupt should be used in the first place. Depending on implementation, interrupts that occur too close together, may be lost! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Interrupts Software Interrupts Some CPU architectures provide an explicit “software interrupt” instruction. This is an instruction that we can use to programmatically force an interrupt. May be used if software sees a need to reset the system or can be used for debugging of code (software debuggers might use it to set breakpoints). The MSP430 does not offer an explicit software interrupt instruction. You can write an invalid password to the WDTCTL register (in the upper 8 bits) to force a reset.  If not using the Watchdog for normal purposes, a Watchdog reset can indicate a software-generated event. Additional flags can also be set to indicate software caused the reset. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Watchdog Timer MSP430 Watchdog Must be periodically reset by software to keep the timer from expiring and resetting the system. Virtually all uC systems have Watchdog timers. The details of how to do a “software check-in” vary from one system to another. In the MSP430, the WDTCNTCL bit in the WDTCTL register must be written as a 1 before the timer expires. The upper 8 bits must be 0x5A (WDTPW). In the MSP430, setting the WDTHOLD bit in the WDTCTL register suspends the Watchdog timer. MSP430 Watchdog can be clocked from SMCLK or ACLK. Clock source can be scaled down before entering the counter. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems Watchdog Timer MSP430 Watchdog In the MSP430, can alternatively be configured as an interval timer. Set the WDTTMSEL bit in the WDTCTL to configure it as a timer. When it expires, no reset occurs and the usual reset vector is not acknowledged. An alternate vector is consulted when the timer overflows (if and only if the maskable interrupts are enabled). Using interrupts or not, a flag is raised. If using interrupts, the hardware will automatically clear this flag (to save software the trouble). If no interrupts, software must poll and clear this flag manually. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Basic Timer1 Some MSP430 varieties have a Basic Timer1 module (not ours). The timer consists of two 8-bit register halves that can be used as independent 8-bit timers or cascaded as a single 16-bit timer. When the timer overflows, a flag is set in a flag register. The flag can trigger an optional, maskable interrupt. If no interrupts, software must poll and manually clear the flag. If using interrupts, hardware automatically clears the flag and calls the associated ISR. Could be used to generate a real-time interrupt. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Real-Time Clock Real-Time Clock If the Basic Timer1 module is present, a Real-Time Clock (RTC) module is also present to provide real measurement of time. Keeping track of “wall time” can be such a common thing to do, the hardware designers provided a hardware module to do it for you. Other uCs might require software keep track of the time based on hardware-generated interrupts. The RTC module can generate an interrupt as an “alarm clock” function. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

ECE 3430 – Intro to Microcomputer Systems MSP430 Timer_A Module All varieties of the MSP430 have a 16-bit Timer_A module! We want separate timing circuitry that will run independent of our program. This ensures more precise timing. Our program run times can be unpredictable due to interrupts! For example, a DELAY subroutine or loop may take longer to complete if it is interrupted by an interrupt. Virtually all microcontrollers have timer facilities. The specific details of how that timer works will vary somewhat depending on the design. The MSP430 Timer_A module is very flexible and can be used as: 1) Plain 16-bit Counter (TAR) 2) Input Capture (Timing reception of inputs) 3) Output Compare (Generating precisely-timed outputs) 4) Real Time Interrupts (Generating a periodic interrupt) 5) Pulse Accumulator (Input pulse timer or event counter) 6) … Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - A 16-bit counter clocked by a ACLK, SMCLK or an external clock. - Has pre-scalar to slow count down. - When overflow occurs (0xFFFF  0x0000), an interrupt can be triggered. - On POR, the counter is cleared to 0x0000. - This counter is readable and writable by software. - When overflow occurs, the timer A interrupt flag (TAIFG) is set in TACTL register. - If configured to generate an interrupt, the ISR is called. - The ISR may need to clear the TAIFG if it is not cleared automatically. - The timer overflow interrupt is maskable, so you must: Ensure the GIE flag in the SR is set (global enable). Ensure the TAIE flag in the TACTL register is set (local enable). Pre-Scalar divide by 1, 2, 4, or 8 Main Timer (TAR) 16-bit Configurable Clock Source    TAIFG TAR High TAR Low Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - The “Timer_A clock source select” bits are located in TACTL (TASSELx). Bit 9 Bit 8 Source 0 0 TACLK (external) 0 1 ACLK (internal) 1 0 SMCLK (internal) 1 1 INCLK (external) - The “Timer_A input divider” bits are located in TACTL (IDx). Bit 7 Bit 6 Pre-Scalar 0 0 1 (fastest overflow rate) 0 1 2 1 0 4 1 1 8 (slowest overflow rate) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - The “Timer_A mode control” bits are located in TACTL (MCx). Bit 5 Bit 4 Mode 0 0 Stop mode (timer is halted, power is conserved) 0 1 Up mode (timer counts up to TACCR0) 1 0 Continuous mode (timer counts up to 0xFFFF) 1 1 Up/down mode (timer counts up to TACCR0 and then down to 0) - Bit 3 of TACTL is unused. - Bits 15-10 of TACTL are unused. - The “Timer_A clear” bit is located in TACTL (TACLR), bit 2. Setting it resets TAR, the clock divider, and the count direction. - The “Timer_A interrupt enable” is located in TACTL (TAIE), bit 1. Setting it “locally” enables interrupts. - The “Timer_A interrupt flag” is located in TACTL (TAIFG), bit 0. It is set by hardware and should be cleared by software (if necessary). Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt Example) Use TAR to pulse P1.4 every 262 ms. Assume 1 MHz SMCLK. 1 MHz/4 = 250 kHz 4 us/count * 65536 counts ~= 262 ms. ORG 0xFFF0 ; initialize “timer” vector table entry DW TAR_ISR ORG 0xFFFE ; initialize “reset” vector table entry DW BEGIN ORG 0xC000 BEGIN: mov.w #0x0400, SP ; set stack pointer (512B RAM device) mov.w #WDTPW+WDTHOLD, &WDTCTL ; stop watchdog timer mov.b #00010000b, &P1DIR ; make P1.4 an output, all others inputs mov.w #TASSEL_2+ID_2+MC_2, &TACTL ; set source, divider, and mode bis.w #TAIE, &TACTL ; enable interrupts locally for module eint ; enable maskable interrupts globally DONE: bis.w #LPM0, SR ; put micro to sleep until interrupt (just stop MCLK/CPU) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt ; ; ISR for timer overflow interrupt. ; Pulse P1.4 (1 -> 0) and clear the TAIFG flag. ; Do-no-damage not required since R4-R15 were not used. TAR_ISR: bis.b #00010000b,&P1OUT ; force P1.4 high bic.b #00010000b,&P1OUT ; force P1.4 low bic.w #TAIFG, &TACTL ; use constants defined in MSP430 headers reti ; always call RETI to leave interrupt service routines 262 ms ISR P1.4 How accurate would you expect this waveform to be? Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2014