1. RL78 POC and LVD
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2. Introduction Purpose Objective Content Learning Time
This course provides an introduction to the RL78 Power-On-Clear and Low Voltage Detector.
Objective
Learn about the RL78 POC and LVD features and its capabilities.
Content
18 pages (including this page)
Learning Time
20 minutes
The purpose of this course is to provide an introduction of the RL78’s Power-on-clear and Low Voltage Detector. Our objectives are to learn about the features and capabilities of these functions. Total learning time is about 20 minutes, so let’s get started.
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3. POC Power-On-Clear
First, we’ll look at the Power-On-Clear functionality.
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4. Power-On-Clear Circuit
Functions
Generates internal reset signal at power on
Compares supply voltage VDD and detection voltage VPOC VDD >= 1.51V ± 0.03V and generates internal reset signal when VDD < 1.50V ± 0.03V
CPU can also be released by LVD, selectable by an option byte
Current consumption already included in STOP mode current
Block Diagram
The Power-On-Clear circuit on RL78 devices is used to control the internal reset signal. It compares the supply voltage with an internal reference voltage of about 1.5 volts and releases or enables the internal reset according to this voltage.
The current consumption of the POC circuit is very low and is included in the stop mode current specification. The POC cannot be controlled by software as it is always on, taking care of the internal reset. Since the reference voltage of the POC at 1.6V is below the minimum supply voltage of the MCU, there is a small undefined range you need to be aware of, which we’ll described next.
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5. Power-On-Clear Circuit
Operation LVD is off VPOC0 to VPOC2 = 0x07
Undefined area
Here we can see the operation of the Power-on-clear circuit. The LVD is not included in this picture as it’s switched off.
As already mentioned, at 1.5V, the internal reset signal will be released. However the minimum supply voltage of the micro is 1.6V, leaving an undefined supply voltage range between 1.5 and 1.6V. Directly after reset, the internal operation of the device stabilizes the flash and the micro reads out the option byte values. This is possible below 1.6 volts and, if only the POC is activated with the LVD switched off, there will be a certain rise time of the supply voltage.
If this can be guaranteed, there is no issue with the undefined area. The same is true in the case of a falling voltage; if the voltage falls into this undefined area we have to switch on the LVD in parallel with the POC, otherwise the device will be running in an undefined range where proper operation cannot be guaranteed.
Only if the supply voltage falls below the POC level of 1.5V will the internal reset signal be active and the micro stops operation. It’s important to note that completely secure operation can only be achieved when the Power-On-Clear Circuit is used in combination with the Low Voltage Detector circuit.
The supply voltage enters the undefined area
If this may happen in the system, the LVD must be used in combination.
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6. LVD Low-Voltage-Detector
Now for a look at the LVD, or Low Voltage Detector.
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7. Low-Voltage-Detector Circuit
Functions
Compares the supply voltage VDD with detection voltage VLVIH, VLVIL and generates a reset or internal interrupt
Detection voltage is selectable by option byte
14 levels (1.63V～4.06V)
Three different operation modes available
interrupt and reset mode
Reset mode
Interrupt mode
Very low power consumption of only 0.1uA
LVD is operating is STOP mode
The low voltage detector circuit is a similar to the POC but has the advantage that it can be configured by an option byte. This means that instead of a fixed level, there are 14 different threshold levels that may be selected. In general, the principal of operation is the same as the POC; the supply voltage is compared to an internal reference voltage and a reset or an internal interrupt is generated if the supply voltage falls or rises through the selected compare voltage.
The low voltage detector has three different operation modes available. The first is “Interrupt and Reset Mode” where an interrupt is initially generated and then the device enters reset after the selected threshold is reached.
The second mode is the “Reset Mode” where the internal reset will be released at a certain voltage and the reset will be active again at the same voltage minus a specified threshold.
The last mode is the pure “Interrupt Mode”, where the reset is released during a rising voltage but during a falling voltage, an interrupt is generated to allow us to put the device into a stable state. Note that the power consumption of the LVD is very low at just 0.1mA in operation mode, so there is no significant increase in the stop mode current with the LVD is operating in Stop Mode.
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8. Block diagram of LVD
Here we see a block diagram of the Low Voltage Detector. Several areas of operation are defined by an option byte; these being the mode, operation and the preselected voltage.
Additional configuration can be done by a Special Function Register. For example the output of the comparator, which compares the internal reference voltage with the supply voltage, can be re-directed via the LVIF flag. Additionally there is a mask flag which shows if the operation of the low voltage detector is enabled, or if it is waiting for the internal stabilization.
There are two additional special function registers which affect “interrupt and reset mode” The LVIF flag controls the selection of input voltages into the comparator, and the LVIMD flag selects the signal to be generated by the low voltage detector; either a direct reset or an internal interrupt.
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9. Option byte for LVD Functions of this register
Select base operation mode of the LVD
Select voltage level of LVD
Address : 000C1H/010C1H 7 6 5 4 3 2 1
VPOC2
VPOC1
VPOC0
LVIS1
LVIS0
LVIMDS1
LVIMDS0
VPOC2-0,LVIS0,1
Set detection voltage by combination
On this slide is the option byte controlling the low voltage detector functionality. The VPOC and the LVIS bits select the LVD detection voltage and the LVIMDS (LVI mode) bits select the three different modes: “interrupt”, “interrupt and reset” or “reset”. These modes cannot be changed later on during operation.
LVIMDS1
LVIMDS0
selection LVD operation mode
Setting prohibited 1
Interrupt mode
interrupt & Reset mode
Reset mode
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10. Low-Voltage Detector levels
Detection voltage levels
When used as reset mode, or interrupt mode
When used as interrupt & reset mode
Detection voltage (TYP.)
Detection voltage (TYP.)
14 levels can be selected.
Here we see the different low voltage detector levels that may be selected by the option byte VPOC and LVIS bits. On the left side are the different voltage levels selectable for “reset” or “interrupt“ modes - where you have two voltages per level - one rising edge voltage (when the supply voltage is increasing) and one falling edge voltage. Typically, there is always a small hysteresis between.
When the “interrupt and reset mode” is used, there are other combinations. We have one rising voltage level where the reset will be released and the micro starts working. But now we have two falling edge levels; a higher level - which will generate the interrupt - and a level below “VLVIL”, which defines the final reset in case of falling supply voltage. More details can be found in each device’s user manual.
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11. LVD control register LVIM
Functions of this register
Write enable for LVIS
Status flags for LVD operation 7 6 5 4 3 2 1
LVIM
LVISEN
LVIOMSK
LVIF
LVISEN
Write enable for LVIS
Disabling rewriting to LVIS 1
Enabling rewriting to LVIS
LVIOMSK
Mask status flag of LVD detection
LVD operation enabled 1
LVD operation waiting
LVIOMSK is set to 1 automatically after LVISEN =1.
After rewriting LVIS, LVD detection needs stabilization.
LVIOMSK =1 during rewriting LVIS and during stabilization.
Therefore after clear LVISEN to 0, LVIOMSK is kept 1 during stabilization time of about 200us to 300us .
Now to the LVD control register “LVIM”. The function of this register is to set the write enable for the LVIS register and additional status flags for LVD operations. The first flag is the LVIS ENable flag. When set to one the LVIS register (the other control register for the low voltage detector) can be re-written, when cleared to zero re-writing is disabled.
The second bit is the LVIO MaSK flag; this is the master enable for LVD operation. When cleared to zero, LVD operation is enabled and, if set to one, LVD operation is waiting – note after re-writing the LVIS register, a stabilization time of 200 to 300 micro seconds is required until the low voltage detector is stable again.
Finally we have the LVIF flag which is the direct output of the comparator and is zero if the LVI is lower than VDD and one if VDD is lower than the LVI.
LVIF
voltage detection status flag
VLVI =< VDD 1
VDD =< VLVI
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12. LVD control register LVIS
Functions of this register
Mode selection (LVIMD)
Voltage level selection (LVILV)
It is possible to write to LVIS register in interrupt & reset mode if LVISEN =1.
In interrupt mode or reset mode it isn't possible to change the value of LVIS.
Interrupt & reset mode
Interrupt mode
Address : FFFAAH After reset : 00H / 01H / 81H
Reset mode
Symbol 7 6 5 4 3 2 1
LVIS
LVIMD
LVILV
Now to the LVIS register which is the last of the LVD low voltage detector control registers. It controls mode selection via the LVIMD bit, and voltage level selection via the LVILV bit. Writing to this register is only possible if LVIS enable is set to one and only in “interrupt and reset mode”.
In “interrupt” or “reset” only modes, it is not possible to write to the LVIS register and the settings are fixed. Because of this, the initial value of the LVIS register will differ depending on the mode pre-selected in the option byte.
In “interrupt” mode the initial value of this register is 0x01, in “reset” mode it is 0x81 and in “interrupt and reset” mode it is set to 0x00. The two flags inside this register are LVIMD, which is the mode selection and used to switch between interrupt mode and reset mode, and LVILV which switches the detection voltage from high level detection voltage to low level detection voltage.
LVIMD
Selection of LVD detection mode
Interrupt mode 1
Reset mode
LVILV
LVD detection voltage level
High-voltage detection level 1
Low-voltage detection level
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13. Different LVD modes Different Objectives and the right LVD mode
Mode to be used A
LVD should be used to substitute an external reset IC.
RESET mode
Reset generation at the preselected voltage. B
Switch device in secure state/standby in case of low voltage.
Interrupt mode
Interrupt generation at the preselected voltage. C
Save important data before reset by low voltage detection.
Interrupt (detection notice) and reset mode
Interrupt generation at the preselected voltage and finally reset generation at reset voltage.
Now we’ll cover the different low voltage detector modes and their uses. Comparing different objectives and choosing the appropriate LVD mode.
Objective A uses the LVD to replace an external reset IC. In this case we should select “reset mode” and the reset will be generated at the preselected voltage.
Objective B is to switch into a secure state or standby if the supply voltage drops out of range, in this case “interrupt mode” is selected. An interrupt is generated at the pre-selected voltage and the device can be switched into a secure state via software, for example into Stop Mode and then wait for the full power down reset coming from the POC circuit.
And the last objective, C, is to save important data before being reset due to a low-voltage detection. In this case the “interrupt (detection notice) and reset mode” should be selected; in which case an interrupt is generated at a pre-selected voltage so the software can save important parameters to e.g. data flash. If an interrupt is generated followed by a reset at the reset voltage, or by a software command, it’s possible to put the device into reset directly after parameter saving is finished.
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14. Example A: external reset IC
Supervise guaranteed voltage range of CPU
To avoid operation outside specified area
Operation condition
LVD setting
frequency : HOCO 32MHz
Voltage : 5V
Option byte 00C1H :“ B”
LVD detection voltage : VLVI5 (rise 2.81V(typ.) fall 2.70(min.))
LVD mode : reset mode
LVD reset release. and CPU start operation.
Reset by LVD
CPU
operable
2.81V(typ.)
2.7V(min.)
LVD
CPU
inoperable
Here’s a more detailed example of objective A operation, where we are replacing an external reset IC. In this case the supply voltage is monitored to determine if it is in the CPU’s valid voltage range. Here the operating state is 5V and the 32MHz internal high speed oscillator is selected.
32MHz operation is only possible down to 2.7V, so the low voltage detector should be set to generate a reset at a minimum 2.7V. For this the option byte at address 0xC1 is set to “ B”, where the detection voltage is set to a typical rising voltage of 2.181V, and a falling voltage of 2.7V thus providing 0.11V hysteresis. The selected mode is “reset mode” where the device is in power-on reset if the supply voltage is below the POC level of 1.5V. Above that it still doesn’t release the internal reset signal but instead switches to “LVD reset” until 2.81V has been passed.
From this point onwards the reset signal is released and the CPU starts operation. Now, if the voltage goes down, reaching 2.7V, the internal reset is set and the device enters “LVD reset mode”. If the voltage decreases further below the power-on reset level, then the device enters “power-on reset mode”. This is one of the easiest ways to use the low voltage detector circuit, with this functionality there is no need to have specific rise or fall times of the supply voltage.
1.51V
POR
->time
CPU state
POR reset
LVD reset
CPU operation
LVD reset
POR reset
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15. Example B: Switch device to standby
Supervise guaranteed voltage range of CPU and set device into standby to avoid operation outside specified area
Operation condition
LVD setting
frequency : HOCO 8MHz
voltage : 3V
Option byte 00C1H :“ B”
LVD detection voltage : VLVI11 (rise 1.88V(typ.)、fall 1.8V(min.))
LVD mode : interrupt mode
Reset release by LVD only rising supply voltage. and start operation CPU.
Cause interrupt by LVD. then switching to standby by software.
CPU
operable
1.88V(typ.)
LVD
1.80V(min.)
Reset by POR. Stopped RTC
CPU
inoperable
In the second example we will switch the device to standby at a specified voltage. In this example the operating frequency is set to 8MHz and the typical supply voltage to 3volt. The LVD detection voltage is set to 1.88volt for rising and to 1.8volt falling and the operation mode is “interrupt mode”.
At the rising supply voltage the internal reset will be released at 1.88volt, at which point the CPU starts operation. The RTC will be initialized from the software and starts running. Now, if the supply voltage falls below the selected 1.8volt level, the reset signal and the interrupt signal will be generated. Using this interrupt the software can, for example, enter Stop Mode where operation is guaranteed down to the power-on reset level of 1.5volt and current consumption will decrease drastically.
Even entering Stop Mode, the RTC continues operating so real-time system information is not lost. Only if the supply voltage falls below the power-on reset level of 1.51volt, will the power-on reset be activated and the real-time counter be reset internally. So only in this case must a re-initialization of the real-time counter be done.
1.51V
POR
->time
CPU state
POR reset
LVD reset
CPU operation
STOP
POR reset
RTC state
POR reset
LVD reset
RTC operation
POR reset
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16. Example C: Save data before reset
Supervise guaranteed voltage range of CPU and save parameters before enter reset.
Operation condition
LVD setting
Option byte 00C1H : “ B”
LVD detection voltage Reset release voltage : VLVI6 2.71V(typ.)
Reset voltage : VLVI8 2.40V(min.)
Interrupt voltage : VLVI6 2.60V(min.)
LVD mode : interrupt (detection notice)& reset mode
frequency : HOCO 8MHz
voltage : 3V
LVD reset release and CPU operation start.
LVD is set to interrupt
Cause interrupt by LVD. Then switching LVD to reset automatically.
saving important data by software.
CPU
operable
2.71V(typ.)
Reset by LVD
2.60V(min.)
LVD
2.40V(min.)
Example C demonstrates saving data before the final reset occurs. Here again the supply voltage is monitored by the LVD and an internal interrupt is generated in the case of low voltage, before a reset finally occurs. This operation example uses an 8MHz internal oscillator with the supply voltage of 3volt and the option byte setting is B.
This results in the detection voltage for the reset release at 2.71volt typical, the reset voltage 2.4volt and the interrupt voltage 2.6volt. The LVI mode is “interrupt and reset mode”. In this example the internal reset is released at a supply voltage of 2.71volt and the CPU starts operation.
Now, if the supply voltage drops crossing the 2.6volt threshold, an internal interrupt is generated. This interrupt can be used to save data and switch the device into a secure state; for example disable some peripherals and save some parameters in the data flash. If the supply voltage then reaches the reset level of 2.4volt, it enters directly into reset mode.
CPU
inoperable
POR
->time
CPU state
POR reset
LVD reset
CPU operation
saving data
LVD reset
POR reset
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17. Summary Power on Clear LVD For more information, visit: Functions
Block Diagram
Operation
LVD
Functions
Block Diagram
Option Bytes
Registers
Operation Modes
For more information, visit:
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18. © 2010 Renesas Electronics Corporation. All rights reserved.