ECE 331 – Digital System Design Multiple-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

ECE 331 - Digital System Design How do you design a combinational logic circuit that adds two 4-bit numbers and a carry-in, and produces a 4-bit sum and a carry-out? Fall 2010 ECE 331 - Digital System Design

How many inputs are there? How do you design a 2-level combinational logic circuit that implements 4-bit addition? How many inputs are there? How many rows in the corresponding truth table? Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design A 4-bit Parallel Adder Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design A 4-bit Parallel Adder One approach would be to construct a truth table with nine inputs and five outputs and then derive and simplify the five output equations. A better method is to design a logic module that adds two bits and a carry, and then connect four of these modules together to form a 4-bit adder. Furthermore, this can easily be extended to n-bits. Fall 2010 ECE 331 - Digital System Design

Two designs for multiple-bit adders: 1. Ripple Carry Adder 2. Carry Lookahead Adder Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Ripple Carry Adder 1 + Carry-in Carry-out Carry ripples from one column to the next Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Ripple Carry Adder An n-bit RCA consists of n Full Adders. The carry-out from bit i is connected to the carry-in of bit (i+1). Simple design Relatively slow Each sum bit can be calculated only after the previous carry-out bit has been calculated. Delay ~ (n) * (delay of FA) Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Ripple Carry Adder FA0 FA1 FA2 C0 C1 C2 … C3 Cn-1 FAn-1 Cn S0 A0 B0 Carry-out Carry ripples from one stage to the next Carry-in LSB position MSB position A1 B1 A2 B2 An-1 Bn-1 S1 S2 Sn-1 Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Multiple-bit Adders The Ripple Carry Adder may be prohibitively slow when the number of bits to add becomes large! The Carry Lookahead Adder provides a significant increase in speed at the cost of additional hardware. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder 1 + Carry Generate Carry End Carry Propagate A B Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder Source: Wikipedia – Adder (Electronics) (http://en.wikipedia.org/wiki/Adder_electronics) Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design 1-bit Full Adder A xor B A . B Source: Wikipedia – Adder (Electronics) (http://en.wikipedia.org/wiki/Adder_electronics) Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder Carry Lookahead Logic uses the concepts of generating and propagating carries. A carry is generated iff both A and B are 1. Generate function: G(A, B) = A . B A carry is propagated if at least one of A or B is 1. Propagate function: P(A, B) = A + B Alt. Propagate function: P*(A, B) = A xor B if Cin = 1 and A = 1 or B = 1 then Cout = 1 Source: Wikipedia – Carry Lookahead Adder (http://en.wikipedia.org/wiki/Carry_look-ahead_adder) Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder For each bit (or stage) of the multiple-bit adder, the carry-out can be defined in terms of the generate and propagate functions, and the carry-in: Ci+1 = Gi + (Pi . Ci) carry-in carry-out Pi* can also be used. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder For bit 0 (LSB): C1 = G0 + (P0 . C0) C1 = (A0 . B0) + ((A0 + B0) . C0) C1 = (A0 . B0) + ((A0 xor B0) . C0) C1 is a function of primary inputs Three-level circuit, therefore 3-gate delay Not a function of previous carries (except C0), therefore no ripple carry. using Pi* Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder For bit 1: C2 = G1 + (P1 . C1) C2 = (A1 . B1) + ((A1 + B1) . C1) C2 = (A1 . B1) + ((A1 + B1) . ((A0 . B0) + ((A0 + B0) . C0)) C2 is a function of primary inputs Three-level circuit, therefore 3-gate delay Not a function of previous carries (except C0), therefore no ripple carry. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder For bit 2: C3 = G2 + (P2 . C2) C3 = G2 + (P2 . (G1 + (P1 . C1)) C3 = G2 + (P2 . (G1 + (P1 . (G0 + (P0 . C0))) C3 is a function of primary inputs Three-level circuit, therefore 3-gate delay Not a function of previous carries (except C0), therefore no ripple carry. Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Carry Lookahead Adder For bit i: Ci+1 = F(G0..Gi, P0..Pi, C0) For i > 4, the silicon area required for the carry circuits becomes prohibitively large. Tradeoff: speed vs. area. How, then, do you build a bigger adder? Fall 2010 ECE 331 - Digital System Design

(Using a hierarchical design) 16-bit Adder (Using a hierarchical design) Block0 Block1 Block2 C0 C8 C16 C24 Block3 C32 S7-0 A7-0 B7-0 A15-8 B15-8 S15-8 A23-16 B23-16 S23-16 A31-24 B31-24 S31-24 Ripple carry (between blocks) Carry Lookahead Adder Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design 4-bit CLA (Standard Component) Fall 2010 ECE 331 - Digital System Design

Multiple-bit Adder/Subtractor Circuit Fall 2010 ECE 331 - Digital System Design

Multiple-bit Adder/Subtractor Could build separate binary adder and subtractor Not common Use 2's Complement integer representation Addition uses binary adder Subtraction uses binary adder with the 2’s Complement representation for the subtrahend Issues Cannot directly convert the most negative n-bit binary number to 2’s complement representation Must detect overflow Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design 4-bit Subtractor Full Adders may be used to form A – B using the 2’s complement representation for negative numbers. The 2’s complement of B can be formed by first finding the 1’s complement and then adding 1. Fall 2010 ECE 331 - Digital System Design

Multiple-bit Adder/Subtractor 1 n – x c -bit adder y Add  Sub control Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Detecting Overflow Fall 2010 ECE 331 - Digital System Design

Detecting Overflow for Addition Overflow occurs if the result is out of range. Overflow cannot occur when adding a positive number and a negative number. Overflow occurs when adding two numbers with the same sign. Two positive numbers → negative number Two negative numbers → positive number Can you write a Boolean expression to detect overflow? Fall 2010 ECE 331 - Digital System Design

Detecting Overflow for Subtraction Overflow occurs if the result is out of range. Overflow cannot occur when subtracting two numbers with the same sign. Overflow occurs when subtracting a positive number from a negative number or a negative number from a positive number. positive # - negative # → negative number negative # - positive # → positive number Can you write a Boolean expression to detect overflow? Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Adder Circuits in VHDL Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL 2 2 2 Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL library ieee; use ieee.std_logic_1164.all; use work.pack.all; ENTITY add3bit IS PORT ( a : IN std_logic_vector(2 downto 0); b : IN std_logic_vector(2 downto 0); cin : IN std_logic; s : OUT std_logic_vector(2 downto 0); cout : OUT std_logic); END add3bit; Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cin1, cin2: std_logic; BEGIN fa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 ); fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 ); fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout ); END struct; Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cin1, cin2: std_logic; BEGIN fa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 ); fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 ); fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout ); END struct; Cin Cout Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cy : std_logic_vector (3 downto 0); BEGIN fa0: fa PORT MAP(a(0),b(0),cy(0), s(0), cy(1)); fa1: fa PORT MAP(a(1),b(1),cy(1), s(1), cy(2)); fa2: fa PORT MAP(a(2),b(2),cy(2), s(2), cy(3)); END struct; Cin Cout Fall 2010 ECE 331 - Digital System Design

Ripple Carry Adder in VHDL ARCHITECTURE struct OF add3bit IS SIGNAL cy : std_logic_vector (3 downto 0); BEGIN Adders: FOR i IN 0 TO 2 GENERATE myfa:fa PORT MAP(a(i),b(i),cy(i),s(i),cy(i+1)); END GENERATE; cout <= cy(3); cy(0) <= cin; END struct; Fall 2010 ECE 331 - Digital System Design

ECE 331 - Digital System Design Questions? Fall 2010 ECE 331 - Digital System Design