1. Computer Organization and Design Arithmetic & Logic Circuits
Montek Singh
Wed, Oct 23, 2013
Lecture 11

2. Topics Arithmetic Circuits Logic Circuits
adder
subtractor
Logic Circuits
Arithmetic & Logic Unit (ALU)
… putting it all together

3. … … … Review: 2’s Complement 8-bit 2’s complement example:
N bits
-2N-1
2N-2 … … … 23 22 21 20
Range: – 2N-1 to 2N-1 – 1
“sign bit”
“binary” point
8-bit 2’s complement example:
= – = – 42
Beauty of 2’s complement representation:
same binary addition procedure will work for adding both signed and unsigned numbers
as long as the leftmost carry out is properly handled/ignored
Insert a “binary” point to represent fractions too:
= – = – 2.625

4. Binary Addition Example of binary addition “by hand”:
Let’s design a circuit to do it!
Start by building a block that adds one column:
called a “full adder” (FA)
Then cascade them to add two numbers of any size… 1
Carries from previous column
A: B:
Adding two N-bit numbers produces an (N+1)-bit result
A B
CO CI S FA
A3 B A2 B A1 B A0 B0
S S S S S0
A B
CO CI S FA
4-bit adder

5. Binary Addition Extend to arbitrary # of bits
n bits: cascade n full adders
Called “Ripple-Carry Adder”
carries ripple through from right to left
longest chain of carries has length n
how long does it take to add the numbers 0 and 1?
how long does it take to add the numbers -1 and 1?
An-1 Bn A2 B A1 B A0 B0
A B
CO CI S FA
A B
CO CI S FA
A B
CO CI S FA
A B
CO CI S FA
Sn Sn S S S0

6. Designing a Full Adder (1-bit adder)
Follow the step-by-step method
Start with a truth table:
Write down eqns for the “1” outputs:
Simplifying a bit (seems hard, but experienced designers are good at this art!)

7. For Those Who Prefer Logic Diagrams
A little tricky, but only 5 gates/bit! Ci
A B S Co
“Carry”
Logic
“Sum”
Logic

8. Subtraction: A-B = A + (-B)
Subtract B from A = add 2’s complement of B to A
In 2’s complement: –B = ~B + 1
Let’s build an arithmetic unit that does both add and sub
operation selected by control input:
~ = bit-wise complement B 1
But what about the “+1”?
A B
CO CI S FA
A A A A0
S S S S S0
B B B B0
Subtract

9. Condition Codes
One often wants 4 other bits of information from an arith unit:
Z (zero): result is = 0
big NOR gate
N (negative): result is < 0
SN-1
C (carry): indicates that most significant position produced a carry, e.g., “1 + (-1)”
Carry from last FA
V (overflow): indicates answer doesn’t fit
precisely:
To compare A and B,
perform A–B and use
condition codes:
Signed comparison:
LT NV LE Z+(NV)
EQ Z
NE ~Z
GE ~(NV)
GT ~(Z+(NV))
Unsigned comparison:
LTU C
LEU C+Z GEU ~C
GTU ~(C+Z)
-or-

10. Condition Codes Subtraction is useful also for comparing numbers
To compare A and B:
First compute A – B
Then check the flags Z, N, C, V
Examples:
LTU (less than for unsigned numbers)
A < B is given by C
LT (less than for signed numbers)
A < B is given by NV
Others in table
To compare A and B,
perform A–B and use
condition codes:
Signed comparison:
LT NV LE Z+(NV)
EQ Z
NE ~Z
GE ~(NV)
GT ~(Z+(NV))
Unsigned comparison:
LTU C
LEU C+Z GEU ~C
GTU ~(C+Z)

11. Latency of Ripple-Carry Adder
(TPD = max propagation delay or latency of the entire adder)
An-1 Bn An-2 Bn A2 B A1 B A0 B0
A B
CO CI S FA
A B
CO CI S FA
A B
CO CI S FA
A B
CO CI S FA
A B
CO CI S FA C …
Sn Sn S S S0
Worse-case path: carry propagation from LSB to MSB, e.g., when adding 11…111 to 00…001.
tPD = (tPD,XOR +tPD,AND + tPD,OR) +(N-2)*(tPD,OR + tPD,AND) + tPD,XOR
 (N) CI
A B S CO
CIN-1 to SN-1
CI to CO
A,B to CO
(N) is read “order N” and tells us that the latency of our adder grows in proportion to the number of bits in the operands.

12. Can we add faster?
Yes, there are many sophisticated designs that are faster…
Carry-Lookahead Adders (CLA)
Carry-Skip Adders
Carry-Select Adders
 See textbook for details

13. Adder Summary
Adding is not only common, but it is also tends to be one of the most time-critical of operations
As a result, a wide range of adder architectures have been developed that allow a designer to tradeoff complexity (in terms of the number of gates) for performance.
Smaller / Slower
Bigger / Faster
Ripple Carry
Carry
Skip
Carry
Select
Carry
Lookahead
Add A B S
Add/Sub A B S
At this point we’ll define a high-level functional unit for an adder, and specify the details of the implementation as necessary.
sub

14. Shifting and Logical Operations

15. Shifting Logic Shifting is a common operation For example:
applied to groups of bits
used for alignment
used for “short cut” arithmetic operations
X << 1 is often the same as 2*X
X >> 1 can be the same as X/2
For example:
X = 2010 =
Left Shift:
(X << 1) = = 4010
Right Shift:
(X >> 1) = = 1010
Signed or “Arithmetic” Right Shift:
(-X >>> 1) = ( >>> 1) = = -1010 1 R7 R6 R5 R4 R3 R2 R1 R0 X7 X6 X5 X4 X3 X2 X1 X0
“0”
SHL1

16. Boolean Operations
It will also be useful to perform logical operations on groups of bits. Which ones?
ANDing is useful for “masking” off groups of bits.
ex & = (mask selects last 4 bits)
ANDing is also useful for “clearing” groups of bits.
ex & = (0’s clear first 4 bits)
ORing is useful for “setting” groups of bits.
ex | = (1’s set last 4 bits)
XORing is useful for “complementing” groups of bits.
ex ^ = (1’s invert last 4 bits)
NORing is useful for.. uhm…
ex # = (0’s invert, 1’s clear)

17. Boolean Unit
It is simple to build up a Boolean unit using primitive gates and a mux to select the function.
Since there is no interconnection between bits, this unit can be simply replicated at each position.
The cost is about 7 gates per bit. One for each primitive function, and approx 3 for the 4-input mux.
This is a straightforward, but not too elegant of a design. Ai Bi Qi
Bool
This logic block is repeated for each bit (i.e. 32 times) 2

18. An ALU, at Last Now we’re ready for a big one! A B Result
An Arithmetic Logic Unit!
That’s a lot of stuff
Flags N,V,C A B
Result
Bidirectional
Shifter
Boolean
Add/Sub
Sub
Bool
Shft
Math Z
Flag

19. Next
Circuits for
Multiplication
Division
Floating-Point Operations