FPro Bus Protocol and MMIO Slot Specification ECE 448 Lecture 17 FPro Bus Protocol and MMIO Slot Specification ECE 448 – FPGA and ASIC Design with VHDL

Required Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 10, FPro Bus Protocol and MMIO Slot Specification Source Code of Examples http://academic.csuohio.edu/chu_p/rtl/fpga_mcs_vhdl.html Basys 3 FPGA Board Reference Manual 7. VGA Port ECE 448 – FPGA and ASIC Design with VHDL

Bus A bus is a communication path that connects multiple components A system bus inside a computer is a bus for a processor to exchange data with memory modules and I/O devices. In a simple setting, the processor functions as a master and the memory modules and I/O devices are slaves. A master initiates the desired transaction, such as a read or write operation, and the designated slave responds accordingly.

SoC Interconnect Instead of using a single centralized bus, an SoC platform provides a distributed communication infrastructure, sometimes referred to as an interconnect The new Xilinx FPGA devices adopt the ARM AMBA AXI protocol for its infrastructure The AXI protocol specifies a point-to-point interface between a single AXI master and a single AXI slave via five channels A master can connect to multiple slaves and vice versa The AXI protocol does not dictate the implementation and leaves it to the SoC vendors. It is capable and flexible. The AXI protocol has been judged too complex by the author of the textbook, and replaced by much simpler FPro bus protocol

FPro Bus The FPro bus is the communication medium shared by the I/O cores of the MMIO and video subsystems The FPro bus is a simple synchronous system bus that supports only read and write operations The processor is the master and can initiate a read or write transaction via the FPro bridge The I/O cores in two subsystems are slaves

Top-level diagram of an FPro system

Signals of the FPro Bus Fp_addr (master to slave). A 22-bit address signal used to identify the destination I/O register or a memory location in the MMIO or video subsystems. The memory space of the FPro I/O subsystem is “word addressable,” which means that the location specified by fp_addr is a 32-bit word. Fp_rd_data (slave to master). A 32-bit signal carrying the read data. Fp_wr_data (master to slave). A 32-bit signal carrying the write data. Fp_rd (master to slave). A 1-bit control signal associated with a read operation. Fp_wr (master to slave). A 1-bit control signal to initiate a write operation. Fp_mmio_cs (master to slave). A 1-bit enable (i.e., “chip select”) signal to activate the MMIO subsystem. Fp_video_cs (master to slave). A 1-bit enable signal to activate the video subsystem.

Timing Diagram of FPro Bus Both FPro bus read and write operations are synchronous and must be completed in one clock cycle

Integrating Custom Logic into the System Adding a wrapping circuit to the custom logic to form a compatible I/O core that can interface with the system's bus Updating the system-level decoding circuit and multiplexing circuit to identify and access the core. The wrapping circuit makes the core resemble a small memory and thus can be addressed and accessed accordingly. It contains a collection of registers (to mimic memory cells), a decoding circuit, and a multiplexing circuit. The decoding circuit decodes the address lines to identify and enable the designated destination register. The multiplexing circuit uses the address lines to select the designated source register and routes the data to the bus.

Block Diagram of a Write Interface

Block Diagram of a Read Interface

Write Interface with FIFO Buffers

Read Interface with FIFO Buffers

Timing Considerations Both FPro bus read and write operations are synchronous and must be completed in one clock cycle

Write Operation At t1, the master issues a write command. At t2, all bus signals are stable after tCQ (clock-to-q delay) and the decoding circuit starts. At t3, the decoded enable signal reaches the designated slave I/O register after the tDEC delay. At t4, the designated slave I/O register samples and stores the write data. Let the clock period be tCLK and the setup time of the register be tSETUP. The circuit must satisfy the timing constraint: tCQ + tDEC + tSETUP < tCLK

Read Operation At t5, the master issues a read command. At t6, all bus signals and I/O register outputs are stable after tCQ and the multiplexing circuit starts. At t7, the designated source read data is routed to the read data lines after the tMUX delay. At t8, the master samples and retrieves the data from bus. The timing constraint becomes tCQ + tMUX + tSETUP < tCLK

MMIO Subsystem

MIMO Slot Interface Specification A slot is a 32-word (25-word) memory module. The slot interface is defined as follows: addr (bus to core). A 5-bit address signal used to identify the 32-bit destination I/O register within the core. rd_data (core to bus). A 32-bit signal carrying the read data. wr_data (bus to core). A 32-bit signal carrying the write data. read (bus to core). A 1-bit control signal activated with the read operation. write (bus to core). A 1-bit control signal to enable the register write. cs (bus to core). A 1-bit enable (i.e., “chip select”) signal to select and activate the core.

Basic MIMO I/O Core Construction Design the custom digital circuit Determine the I/O register map for the slot interface Derive the wrapping circuit Develop the software driver

An Entity Declaration of an MMIO Core The UART Core Example

GPO Core

GPI Core

Timer Core Development 48-bit Timer Logic

Timer Core The processor interacts with the counter as follows: retrieve (i.e., read) the 48-bit counter value. set or reset (i.e., write) the go signal to resume or pause the counting. generate (i.e., write) a pulse to clear the counter to 0. Register Map offset 0 (lower word of the counter) – bits 31 to 0: 32 LSBs of the counter offset 1 (upper word of the counter) – bits 15 to 0: 16 MSBs of the counter offset 2 (control register) –bit 0: the go signal of the counter –bit 1: the clear signal of the counter

Timer Core in VHDL (1)

Timer Core in VHDL (2)

Timer Core in VHDL (3)

MMIO Controller The MMIO subsystem contains up to 64 (i.e., 26) I/O cores, each with up to 32 (i.e., 25) I/O registers. From processor's perspective, the entire subsystem can be considered as a stand-alone I/O module with a 211-bit address space, in which 6 MSBs are the module bits used to identify a core and 5 LSBs are offset bits used to identify an I/O register within the core. MMIO controller utilizes 6 module bits to select and enable the designated I/O core and to perform subsystem-level decoding and multiplexing. The decoding circuit generates 64 enable signals, each connecting to the chip-select signal (cs) of an I/O core. The multiplexing circuit is a 64-to-1 multiplexer and routes the read data from the designated I/O core to the FPro bus.

Data Types and Constant Declarations in chu_io_map

VHDL Code of the MMIO Controller (1)

VHDL Code of the MMIO Controller (2)

Vanilla FPro System

VHDL Code of the Vanilla MMIO Subsystem (1)

VHDL Code of the Vanilla MMIO Subsystem (2)

VHDL Code of the Vanilla MMIO Subsystem (3)

VHDL Code of the Vanilla MMIO Subsystem (4)

MicroBlaze Micro Controller System (MCS) A 32-bit soft-core processor provided by Xilinx Constructed from the logic cells of the FPGA device Highly configurable, with a variety of optional features, such as instruction cache, data cache, memory management unit, and floating-point unit Utilizes the AXI interface to communicate with other IP cores Available together with a large collection of pre-designed IP cores, including memory controllers, general I/O peripherals, and specialized hardware accelerators A complete MicroBlaze system that contains a pre-configured MicroBlaze processor, local memory, and a tightly coupled I/O module, which contains a set of standard I/O peripherals and a “bus port.”

MicroBlaze MCS Instantiation & Configuration Can be instantiated with Vivado's the IP catalog utility For the purpose of this class, it should be configured as follows: Set the memory size to 128 KB. This helps to run larger programs. Enable the I/O bus port of the I/O module. The bus port will be used to bridge the FPro bus. De-select all other I/O peripherals. The I/O modules will be constructed from scratch in the MMIO subsystem. Details in the Textbook Appendix A.4

MicroBlaze MCS I/O Bus Unlike the full-featured MicroBlaze, MCS does not support the AXI interface. It uses a simple I/O bus port, which is port of the I/O module, to communicate with external components. A 30-bit byte address space, from 0xc0000000 to 0xffffffff is allocated for this purpose. The MCS I/O bus is a synchronous bus.

Signals of the MicroBlaze MCS I/O Bus IO_Address (master to slave). It is a 32-bit address signal. Note that the memory space of the MCS I/O module is “byte addressable,” which means that the location specified by IO_Address is a byte. IO_Read_Data (slave to master). It is a 32-bit signal carrying the read data. IO_Write_Data (master to slave). It is a 32-bit signal carrying the write data. IO_Addr_Strobe (master to slave). It is a 1-bit control signal to indicate whether IO_Address is valid. IO_Read_Strobe (master to slave). It is a 1-bit control signal associated with a read operation. IO_Write_Strobe (master to slave). It is a 1-bit control signal to initiate a write operation. IO_Byte_Enable (master to slave). It is a 4-bit control signal to indicate which bytes of IO_Write_Data are used in the write operation. IO_Ready (slave to master). It is a 1-bit status signal from the slave to indicate whether the designated transaction is completed.

Representative Timing Diagram of the MCS I/O Bus

MCS-to-FPro Bridge (1)

MCS-to-FPro Bridge (2)

The Address Translation bits 31 to 24: used to decode the FPro I/O module base address. bit 23: used to distinguish the two subsystems and generate the chip-select signals. bits 22 to 2: used to identify an I/O register or a memory location in the MMIO and video subsystems. They form the 21-bit FPro address. bits 1 to 0: not used because FPro system uses “word address.”

Vanilla FPro System (1)

Vanilla FPro System (2)

Vanilla FPro System (3)

Vanilla FPro System (4)

Vanilla FPro System (5)