1. BUSES
FUNCTIONAL UNITS
Ch.Ramesh
Embedded Systems

2. 1. Processor memory bus (front system bus) FSB 2. I/O buses (channel)
BUS: it serves as shared communication link between the subsystems of a computer. i.e. the CPU, memory, and I/O devices.
Types of Buses:
1. Processor memory bus (front system bus) FSB
2. I/O buses (channel)
FSB : The processor memory bus acts as a pipe between the processor and memory, which includes data, address and control bus.
It offers very high speed and low latency
The processor memory bus is matched to the memory system it connects to maximize memory processor band width.
I/O bus: it is normally lengthy with many types of devices connected to them.
They have different data transfer rates, bandwidths and use different clock rates.
Ch.Ramesh
Embedded Systems

3. CPU memory bus ( synchronous )
I/O devices are usually not directly interfaced to memory instead they are connected to processor memory through the bus adaptor i.e. PCI, PCI-X, SCSI
Typical Bus Implementation
CPU memory bus ( synchronous )
cache
CPU
Bus
Adaptor
Address
transition
registers
DMA
Main
Memory
Io bus (asynchronous) IO
controller
Graphics
NETWORK
Other configuration
Ch.Ramesh
Embedded Systems

4. TYPICAL READ TRANSACTION
Basic bus Transactions :
The transactions are 1. Write to memory 2. Reading fro memory
Put address out and De-assert read
Memory puts data out and De-assert read
Clock
Address bus
Data
Read
Wait
TYPICAL READ TRANSACTION
Ch.Ramesh
Embedded Systems

5. TYPICAL READ TRANSACTION
Master asserts address bus
Master asserts address bus
t0 master obtains control and waits for slave to decode address
Read
Request
t3 and t4 release events
Ack to t1 t2 t3 t4
t1: master asserts request line
t2: slave asserts Ack ( data received)
Ch.Ramesh
Embedded Systems

6. Bus Design Decisions: S.No. Option Better performance Lower cost 1
Bus width
Separate address and data lines
Multiplex address and data lines 2
Number of bus lines
Wider is faster
Narrower is cheaper 3
Transfer size
Multiple words have less bus overhead
Single word transfer has simpler logic 4
Bus masters
Multiple words have less bus overheads.
Single no arbitration 5
Split transaction
Separate request and reply packets get higher bandwidth
No continuous connection is cheaper and has lower latency 6
Clocking
Synchronous
Asynchronous
Ch.Ramesh
Embedded Systems

7. Bus Options:
Bus Masters: A bus master is device on the bus that has the power to initiate a transaction.
The CPU is always a bus master and I/O devices can also be bus masters
With multiple masters an arbitration scheme is required to determine who gets the control of the bus.
Split Transactions: The bus is busy from the time the data requested to the time the request is completed.
In systems where multiple bus masters, there split transactions provide an improvement in band width.
In split transactions the read request is sent and the bus is released while the data is prepared.
Ch.Ramesh
Embedded Systems

8. Synchronous Bus:
It requires a fine protocol for addresses and data relative to a global clock that all devices agree upon.
Signals are valid only certain points on clock waveform usually the rising edge or falling edge
Ch.Ramesh
Embedded Systems

9. Performance Metrics : Throughput: Response Time:
Through put is usually called the IO band width.
This measures the amount of data a particular I/O device can transfer in a given period of time.
Response Time:
This is also called the I/O latency.
It measures the time taken between the request placed on a device queue and the time that service is completed.
It includes the time of waiting in the queue and the usual service time.
Through put can be increased by adding additional disks to a system.
Allowing more requests to be serviced at a given time.
Requests would likely spend less time.
For minimum response time queues must be kept empty so that an incoming request can be serviced as soon as it enters.
Producer
Receiver
queue
Ch.Ramesh
Embedded Systems

10. BACK PLANE BUS SYSTEM:
The backplane bus interconnects processors, data storage, and peripheral devices in a tightly coupled hardware configuration.
The system bus must be designed to allow communication between devices on the bus without disturbing the internal activities of all the devices attached to the bus.
Timing protocols must be established to arbitrate among multiple requests.
Operational rules must be set to ensure orderly data transfers on the bus.
Ch.Ramesh
Embedded Systems

11. Data Transfer Bus (DTB) ( Data, Address, And Control Lines)
controller
System clock
Driver, daisy
Chain driver
Power driver,
Bus timer,
arbiter
CPU
board
Processor
and cache
Memory
array
Memory
board
Functional
module
Functional
module
Interface
logic
Interface
logic
Interface
logic
Slot - 1
Slot – k-1
Slot - k
Back plane busses, system interface, slot connections to various functional boards
Data Transfer Bus (DTB) ( Data, Address, And Control Lines)
DTB arbitration bus
Interrupt and synchronization bus
Utility Bus
Ch.Ramesh
Embedded Systems

12. Typical time sequence for information transfer between a master and a slave
Master Slave
Send request to bus
Bus allocated
Load address / data on bus
4. Slave selected after signal is stabilized.
5. Signal data transfer
6. Take stabilized data
7. Acknowledge data taken
8. Knowing data taken remove data and free bus
9. Knowing data removed
10. Signal transfer completed and free the bus
11. Send the next bus request.
Ch.Ramesh
Embedded Systems

13. Synchronous bus timing with fixed length clock signals for all devices
DATA BIT
DATA LINE
MASTER
DATA READY
SLAVE
DATA ACCEPT
Synchronous bus timing with fixed length clock signals for all devices
DATA LINE
DATA BIT
DATA BIT
DATA BIT
MASTER 3 3 1 1
DATA READY
SLAVE
DATA ACCEPT 2 4 2 4
Asynchronous bus timing using four edge handshaking with variable length signals
Ch.Ramesh
Embedded Systems

14. Each potential master can send a bus request.
CENTRAL ARBITRATION
A special signal line is used to propagate a bus grant signal level from the first master to last master.
Each potential master can send a bus request.
A fixed priority is set in a daisy chain from left to right. Only when the device on the left do not request bus control can a device be granted bus tenure.
Ch.Ramesh
Embedded Systems

15. BUS TRANSACTION TIMING
Master - 1
Master - 2
Master - n
DATAA TRANSFER BUS
CENTRAL
BUS
ARBITER
BUS BUSY
DAISY CHAINED BUS ARBITRATION
BUS REQUEST
BUS TRANSACTION TIMING
BUS GRANT
BUS
BUSY
Ch.Ramesh
Embedded Systems

16. INDEPENDENT REQUESTS AND GRANTS
Instead of using shared request and grant lines , multiple bus request and bus grant signals can be independently provided for each potential master.
The arbitration among potential masters is carried out by central arbiter.
The advantage of using independent requests and grants in bus arbitration is their flexibility and faster arbitration .
The draw back is that large number of arbitration lines are required.
Master - 1
Master - 2
Master - n
DATAA TRANSFER BUS
CENTRAL
BUS
ARBITER
BG1
BR1
BR2
BRN
BG2
BGN
BUS BUSY
Ch.Ramesh
Embedded Systems

17. DISTRIBUTED ARBITRATION:
Each potential master is equipped with its own arbiter and unique arbitration number.
The arbitration number is used to resolve the arbitration competition. Parallel contention arbitration is used to determine which device has the highest arbitration number.
Each potential master can send the arbitration numbers to the shared bus request/grant line through their respective arbiters.
Master-1
Master-2
Master-n
Arbiter-1
Arbiter-2
Arbiter-n AN
DATA TRANSFER BUS BB
Ch.Ramesh
Embedded Systems

18. Future bus + Standards Major objectives
Architecture , processor , and technology independent toward an open standard for all designers.
Fully asynchronous timing protocol or data transfer.
Optional source synchronized ( Packet) protocol for high speed block data transfers.
Fully distributed parallel arbitration protocols to support a rich variety of bus transactions i.e. broadcast, broadcall, three-party transactions.
Ch.Ramesh
Embedded Systems

19. 5. Support for high reliability and fault tolerant protocols.
6. Use of multi mechanism for locking modules and avoidance of dead lock or live lock.
7. Circuit switched and split transaction protocols and support for memory commands and consistent priority treatment plus support of a distributed clock synchronization protocol
8. Support of 32 or 64 bit addressing with dynamically sized data buses to support wide variety of bandwidths.
Ch.Ramesh
Embedded Systems

20. Central arbitration lines Miscellaneous lines
Signal lines Proposed for Future Bus Standards
The command lines
Capability lines
Arbitration bus lines
Central arbitration lines
Miscellaneous lines
Ch.Ramesh
Embedded Systems

21. Address lines and Data lines :
Command lines:
They carry command information from the master to one or more slaves. The status lines are used by the slaves to respond to the master.
Capability lines:
They are used to declare special bus transactions. Every byte of lines is protected by at least one parity check line.
Address lines and Data lines :
64 bit address lines are multiplexed with the lower order 64 bit data lines. Additional data lines are added to form a data path up to 256 bits wide.
Ch.Ramesh
Embedded Systems

22. The bus tenure lines are used to coordinate transfer of bus control.
Synchronization signals are used to coordinate exchange of the address , command, capability status and data during a bus transaction.
The address handshake lines and data hand shake lines are used by both master and slave.
The bus tenure lines are used to coordinate transfer of bus control.
Arbitration bus lines
They carry a number which signifies the precedence of competitors during the arbitration process. Synchronous and condition lines are used to coordinate handshaking and special conditions.
Ch.Ramesh
Embedded Systems

23. Central arbitration lines:
They are used by central arbiter in case of control bus control is desired.
Miscellaneous lines:
They are needed to indicate geographical addresses and to initialize the buses during system reset or after live insertion of a card. The total number of bus lines are ranges from 91, 127, 199, 343 for 32, 64, 128 and 256 bit future bus+ standards.
Ch.Ramesh
Embedded Systems

24. FUNCTIONAL UNNITS

25. Various Functional Units Include Instruction cache
Memory management unit
Data cache
Bus control unit
RISC integer unit
Floating point control unit
Graphics unit
Pipelined adder unit
Pipelined multiplier unit
Ch.Ramesh
Embedded Systems

26. Memory Management unit
Instruction cache
The instruction cache has 4kB organized as a two set associate memory with 32bytes per block. It transfers 64 bits for clock cycle.
Data cache
It is two set associated memory of 8kB. It transfers 128 bits per clock cycle, 640MBytes at 40MHz. Write back policy is used. Caching can be inhibited by software if needed.
Bus control unit
The bus control unit coordinate 64 bit data transfer between the chip and outside world.
Memory Management unit
It implements the protected 4KByte paged virtual memory of 232 bytes through translation look aside buffer (TLB)
Integer unit
The RISC integer unit executes load, store, integer, bit, and control instructions and fetches instructions for floating point control unit also.
Floating point units
There two floating point units i.e. the adder and multiplier they can be used separately or simultaneously under the coordination of floating point control unit.
For dual operation floating point instructions such as add and multiply and subtract and multiply uses both the multiplier and adder units in parallel.
Ch.Ramesh
Embedded Systems

27. Various functional units of a computer
External Address 32
INSTRUCTION
CACHE
(4k BYTES)
MEMORY
MANAGEMENT
UNIT
DDATA
(8k BYTES)
BUS
CONTROL UNIT
Core Registers
RISC
Integer Unit
FP Registers
Floating Point
Control Unit
Merge Registers
Graphics Unit
Pipeline
Adder Unit
Multiplier Unit T Kr Ki
Data Address
Instruction Address
Cache Data
128 64
FP Instruction
Core Instruction 32 32 32 32
External Data 64 64 64 64
Dest-1
src-1
src-2
Various functional units of a computer
Ch.Ramesh
Embedded Systems

28. DUAL OPERATION IN FLOATING POINT UNITS
Source 1
Source 2 kr
Destination
Op1
Op2
Result
Multiply unit (sp)
Kr X Source 2
Op1
Op2
Result
Adder unit
Kr X Source 2 + Source 1
DUAL OPERATION IN FLOATING POINT UNITS
Ch.Ramesh
Embedded Systems

29. Floating point units
There two floating point units i.e. the adder and multiplier they can be used separately or simultaneously under the coordination of floating point control unit.
For dual operation floating point instructions such as add and multiply and subtract and multiply uses both the multiplier and adder units in parallel.
The integer unit and floating point control unit can execute concurrently i.e. one integer and one floating point at the same time.
The floating point unit operates with single-precision (32Bit) and double precision (64-bit) operands.
Graphics unit
It executes integer operations corresponding to 8, 16, 32 bit pixel data types.
The unit supports three dimensional drawing in a graphics frame buffer. With color intensity, shading, and hidden surface elimination.
The merge register is used only by vector integer instructions. The register accumulates the results of multiple data addition operations.
Ch.Ramesh
Embedded Systems