ECE 434 Advanced Digital System L13

Slides:



Advertisements
Similar presentations
CPE 201 Digital Design Lecture 25: Register Transfer Level Design (2)
Advertisements

Lecture 23: Registers and Counters (2)
Register Transfer Level
1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) ‏ Our design methodologies do not scale well to real-world problems.
Computing Machinery Chapter 7: Register Transfers.
Give qualifications of instructors: DAP
FIGURES FOR CHAPTER 19 STATE MACHINE DESIGN WITH SM CHARTS
Nonlinear & Neural Networks LAB. CHAPTER 19 State Machine Design with SM charts 19.1 State Machine Charts 19.2 Derivation of SM Charts 19.3 Realization.
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL.
3/20/20091 More State Machines. Multiple processes.
The Control Unit: Sequencing the Processor Control Unit: –provides control signals that activate the various microoperations in the datapath the select.
1 COMP541 Sequencing and Control Montek Singh Mar 29, 2007.
10/20/20081 Lab 6 – More State Machines. Multiple processes.
10/13/ Lab 6 - Algorithmic State Machines ECE238L 10/13/2009.
Contemporary Logic Design Arithmetic Circuits © R.H. Katz Lecture #24: Arithmetic Circuits -1 Arithmetic Circuits (Part II) Randy H. Katz University of.
Lab 10 RT methodology (cont’d) Example 1 – a counter Example 2 – a repetitive-adder multiplier.
1 Lecture 4: Arithmetic for Computers (Part 4) CS 447 Jason Bakos.
Registers and Counters
Chapter 6-2 Multiplier Multiplier Next Lecture Divider
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 21 Multiplier Example Example: (101 x 011) Base 2 Note that the partial product summation.
Chap 8. Sequencing and Control. 8.1 Introduction Binary information in a digital computer –data manipulated in a datapath with ALUs, registers, multiplexers,
Instructor: Yuzhuang Hu Another Design Example: PIG (Chapter 7-10) PIG is a single dice game. Two players roll the dice in turns. When.
ENG241 Digital Design Week #8 Registers and Counters.
BR 1/991 Dice Game Implementation Why was dice game implemented in three 22V10 PLDs? What are the resources needed by the Dice Game? –Outputs: 6 for dice.
Chapter 3 Digital Logic Structures. 3-2 Combinational vs. Sequential Combinational Circuit always gives the same output for a given set of inputs  ex:
Digital Logic Design (CSNB163)
BR 1/991 Dice Game (Chapter 22) The dice game in Chapter 22 is a good example of a Finite State Machine controlling a Datapath. –The combined FSM/Datapath.
Digital System Design using VHDL
Department of Communication Engineering, NCTU 1 Unit 4 Arithmetic and Logic Units.
CEC 220 Digital Circuit Design Dice Game Wed, April 06 CEC 220 Digital Circuit Design Slide 1 of 15.
RTL Hardware Design by P. Chu Chapter 9 – ECE420 (CSUN) Mirzaei 1 Sequential Circuit Design: Practice Shahnam Mirzaei, PhD Spring 2016 California State.
1 강의노트 09 Logic Design with ASM Charts: Based on Digital Systems Design Using VHDL, Chapter 5, by Charles H. Roth, Jr.
Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.
Design at the Register Transfer Level Algorithmic State Machines 07.
Digital Design with SM Charts
Sequential Logic Design
EKT 221 : DIGITAL 2.
Multiplication and Division basics
CHAPTER 18 Circuits for Arithmetic Operations
Digital Electronics Multiplexer
Lecture 11 Registers and Counters
Registers and Counters
Instructor: Alexander Stoytchev
SLIDES FOR CHAPTER 12 REGISTERS AND COUNTERS
Digital Electronics Multiplexer
Lecture 16 Arithmetic Circuits
Arithmetic and Logic Units
Multipliers Multipliers play an important role in today’s digital signal processing and various other applications. The common multiplication method is.
Principles & Applications
Digital Systems Section 14 Registers. Digital Systems Section 14 Registers.
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Instructor: Alexander Stoytchev
Digital System Design Review.
KU College of Engineering Elec 204: Digital Systems Design
ECE 434 Advanced Digital System L12
CPE/EE 422/522 Advanced Logic Design L15
Unsigned Multiplication
Arithmetic Logical Unit
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN
CPE/EE 422/522 Advanced Logic Design L17
Instructor: Alexander Stoytchev
Reading: Study Chapter (including Booth coding)
REGISTER TRANSFER LEVEL (RTL) DESIGN Using ASM CHART
ECE 434 Advanced Digital System L11
Montek Singh Mon, Mar 28, 2011 Lecture 11
CHAPTER 18 Circuits for Arithmetic Operations
Design of Networks for Arithmetic Operation
Forward Design by state transition table, and state graph
Instruction execution and ALU
Presentation transcript:

ECE 434 Advanced Digital System L13 Electrical and Computer Engineering University of Western Ontario

Review: Block Diagram of a Binary Multiplier Ad – add signal // adder outputs are stored into the ACC Sh – shift signal // shift all 9 bits to right Ld – load signal // load multiplier into the 4 lower bits of the ACC and clear the upper 5 bits 15/11/2018

Review: State Graph for Binary Multiplier 15/11/2018

Review: Multiplier Control with Counter (cont’d) Increment counter each time a shift signal is generated Generate K after n-1 shifts occured 15/11/2018

Review: Array Multiplier What do we need to realize Array Multiplier? AND gates = ? FA = ? HA = ? 15/11/2018

Review: Array Multiplier (cont’d) 15/11/2018

Review: Multiplication of Signed Binary Numbers How to multiply signed binary numbers? Procedure Complement the multiplier if negative Complement the multiplicand if negative Multiply two positive binary numbers Complement the product if it should be negative Simple but requires more hardware and time than other available methods 15/11/2018

Review: Multiplication of Signed Binary Numbers Four cases Multiplicand is positive, multiplier is positive Multiplicand is negative, multiplier is positive Multiplicand is positive, multiplier is negative Multiplier is negative, multiplicand is negative Examples 0111 x 0101 = ? 1101 x 0101 = ? 0101 x 1101 = ? 1011 x 1101 = ? Preserve the sign of the partial product at each step If multiplier is negative, complement the multiplicand before adding it in at the last step 15/11/2018

Review: 2’s Complement Multiplier 15/11/2018

State Graph for 2’s Complement Multiplier 15/11/2018

Faster Multiplier Move wires from the adder outputs one position to the right => add and shift can occur at the same clock cycle 15/11/2018

State Graph for Faster Multiplier 15/11/2018

Behavioral Model for Faster Multiplier 15/11/2018

Behavioral Model for Faster Multiplier 15/11/2018

Command File and Simulation 15/11/2018

Test Bench for Signed Multiplier 15/11/2018

Digital design with SM Charts State graphs used to describe state machines controlling a digital system Alternative: use state machine flowchart 15/11/2018

State Machine Charts SM chart or ASM (Algorithmic State Machine) chart Easier to understand the operation of digital system by examining of the SM chart instead of equivalent state graph SM chart leads directly to hardware realization 15/11/2018

Components of SM charts 15/11/2018

SM chart is constructed from SM blocks State S1 is entered => Z1 and Z2 become 1 if X1=0 Z3 and Z4 become 1 if X1=1 and X3=0 Z5 become 1 15/11/2018

Equivalent SM Blocks 15/11/2018

Equivalent SM Charts for Comb Networks 15/11/2018

Block with Feedback 15/11/2018

Equivalent SM Blocks 15/11/2018

Converting a State Graph to an SM Chart 15/11/2018

Derivation of SM Charts Binary Multiplier Dice Game 15/11/2018

SM Chart for Binary Multiplier 15/11/2018

VHDL for Multiplier SM Chart (I) 15/11/2018

VHDL for Multiplier SM Chart (II) 15/11/2018

Electronic Dice Game Block diagram 1. Two counters simulate the roll of dice (1-6); sum of two counters is in range of 2-12 2. Reset – initiate new game 3. Rb – roll button; when the roll button is pressed the counters count at high speed; when the button is released, the values of counters are displayed and game can proceed. 15/11/2018

Electronic Dice Game - Description First roll player wins if the sum is 7 or 11 player loses if the sum is 2, 3 or 12 otherwise, the sum obtained in the first roll is referred as a point, and player must roll the dice again Second roll (or subsequent roll) player wins if the sum equals the point player loses if the sum is 7 otherwise, player rolls again until she/he finally wins or loses 15/11/2018

Flowchart for Dice Game 15/11/2018

Control Network for Dice Game Input signals to the control network D7 – 1 if the sum of the dice is 1 D711 – (7 or 11) D2312 – (2, 3, 12) Eq – 1 if the sum equals the number stored in the point register Rb – 1 when the roll button is pressed Reset – 1 when the reset button is pressed Output from the control network Roll=1 – enables the dice counters Sp=1 – sum is stored in the point register Win=1 – turns on win light Lose=1 – turns on lose light 15/11/2018

SM Chart for Dice Game 15/11/2018

State Graph for Dice Game 15/11/2018

Behavioral Model for Dice Game (1) 15/11/2018

Behavioral Model for Dice Game (2) 15/11/2018

To Do Read chapters 4.1, 4.2, 4.3 Do homework #4 15/11/2018