1. Digital Design with SM Charts
발표자 : 김 태 완
발표일자 :

2. Contents SM Charts properties Derivation of SM Charts
Implementation of the Dice game
Alternative realizations for SM Charts using Microprogramming
Linked State Machine

3. SM Charts properties ASM (Algorithmic State Machine)
Often used to design control units for digital systems
Useful in the H/W design of digital systems
Easier to understand the operation
Leads directly to a hardware realization

4. Components of SM chart xxx (c) Conditional (a) State box
State_name/
Output list
xxx
Optional
State code
(a) State box
condition 1
(true branch)
(false branch)
(b) Decision box
Conditional
Output list
(c) Conditional
Output box

5. Example of an SM chart S1/Z1Z2 SM block n exit paths One entrance path
One state SM
block
Link
Path a 1 X1
Link
Path b X3
Z3 Z4 1 1 X2 Z5 1 2 3 n
n exit paths

6. Equivalent SM Blocks S1/Z1 Z2=1 if X1=0 S2 if X2=0 S3 if X2=1 S1/Z11 X1 1 X2 1 Z2 X1 X1 1 X2 Z2 Z2
S2/
S3/
S2/
S3/
(a)
(b)

7. Equivalent SM Charts for a combinational Network1
S0/ A 1 1
A+BC C 1 B Z1 Z1
(a)
(b)
Z1=A+A`BC=A+BC

8. SM Block with feedback Every valid combination of input variables
must have exactly one exit path defined
No internal feedback within an SM block
is allowed
S0/
S0/ x x 1 1
(a) Incorrect
(b) Correct

9. Conversion of a state Graph to an SM chart
1/0
1/0
So/ Za
S1/ Zb
S2/ Zc
1/Z2
0/0
(a) State graph
0/0
0/Z1 00
S0/Za
Link 1
(b) Equivalent SM chart x 1 01
S1/Zb
Link 2 x 1
Link 3
S2/Zc 11 x 1 Z1 Z2

10. Derivation of SM Charts
First, draw a block diagram of the system we are controlling
Next, define the required input and output signals to the control network
Then, construct an SM char that tests the input signals and generates the proper sequence of output signals

11. EX1.SM Chart for Binary MultiplierSt 1
Load
St : start, M : LSB, Ad : add,
Sh : shift, K : last shift
S1/ 1 M Sh Ad K
S2/Sh 1 1 K
S3/Done

12. EX1.VHDL for SM Chart Entity Mult is port(CLK,St,K,M: in bit;
when 1 => if M=‘1’ then M (state 1)
Ad<=‘1’ ;
Nextstate<=2;
else M’
Sh<=‘1’;
if K=‘1’ then Nextstate<=3; K
else Nextstate<=1; K’
end if
when 2 => Sh<=‘1’; (state 2)
if K=‘1’ then Nextstate<=3; K
else Nextstate<=1; K`
when 3 => Done <= ‘1’; Nextstate <= 0; (state 3)
end case;
end process;
process(CLK)
begin
if CLK = ‘1’ then
State <= Nextstate; update state on rising edge
end if ;
End SMbehave ;
Entity Mult is
port(CLK,St,K,M: in bit;
Load,Sh,Ad,Done: out bit);
End Mult;
Architecture SMbehave of Mult is
signal State, Nextstate : integer range 0 to 3;
begin
process(St, K, M, State)
Load<=‘0’ ; Sh<=‘0’ ; Ad<=‘0’ ;
case State is
when 0 => if St=‘1’ then (state 0) --- St
Load<=‘1’;
Nextstate<=1;
else Nextstate<=0; St’

13. EX2.Dice Game Rule The player wins if the sum is 7 or 11
The player loses if the sum is 2,3,12
otherwise, the sum is referred to as a point and roll again
The second or subsequent,
the player wins if the sum equals the point
the player loses if the sum is 7,
Otherwise, the player roll again until player wins or loses

14. EX2.Dice Game <Block Diagram for Dice Game> DiceGame Module
Display
Display
Control Rb
1-to-6
Counter
1-to-6
Counter
Roll
Reset
Adder D7
Test
Logic
Win
Sum
D711
D2312
Point
Register
Lose
Comparator Eq Sp
<Block Diagram for Dice Game>

15. Flowchart for Dice Game
Roll dice Y
Sum =
7 or 11 N N
Sum =
2,3,12 Y
Store sum in
Point register
Roll dice Y
Sum =
Point N
Sum = 7 N Y
Win
Lose Y
Reset N N
Reset Y

16. SM chart for Dice Game S0 : No button S1 : Button Pressed S2 : WinRb 1
Roll
S1 / 1 Rb
Press and Release 1
D711 1
D2312
S3/Lose
S0 : No button
S1 : Button Pressed
S2 : Win
S3 : Lose
S4 : No button
S5 : Button Pressed Sp
Reset
S4 / 1 Rb 1
Roll
S5 / 1 Rb 1 Eq
S2 / Win D7 1
Reset 1

17. Behavioral Model for Dice Game
Entity DiceGame is
port (Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
End DiceGame;
Library BITLIB;
Use BITLIB.bit_pack.all;
Architecture DiceBehave of DiceGame is
signal State, Nextstate: integer range 0 to 5
signal Point: integer range 2 to 12;
signal Sp: bit;
begin
process(Rb, Reset, Sum, State)
Sp<=‘0’ ; Roll<=‘0’ ; Win<=‘0’ ; Lose<=‘0’ ;
case State is
when 0 => if Rb=‘1’ then Nextstate<=1; end if;
when 1 =>
if Rb=‘1’ then Roll<=‘1’;
elsif Sum =7 or Sum=11 then Nextstate<=2;
elsif Sum=2 or Sum=3 or Sum=12 then
Nextstate<=3;
else Sp<=‘1’ ; Nextstate<=4;
end if;

18. Behavioral Model for Dice Game
when 2 => Win<=‘1’;
if Reset=‘1’ then Nextstate<=0; end if ;
when 3 => Lose<=‘1’;
when 4 => if Rb=‘1’ then Nextstate<=5; end if
when 5 =>
if Rb=‘1’ then Roll<=‘1’;
elsif Sum=7 then Nextstate<=3 ;
else Nextstate<=4;
end if;
end case;
end process;
process(CLK)
begin
if rising_edge(CLK) then
state<=Nextstate;
if Sp=‘1’ then Point<=Sum; end if;
end DiceBehave;

19. Complete Dice Game Entity Game is
port(Rb, Reset,Clk : in bit; Win, Lose: out bit);
end Game;
Architecture Play of Game is
component Counter
port(Clk, Roll : in bit; Sum :
out integer range 2 to 12);
end component;
component Dicegame
port(Rb, Reset,Clk : in bit;
Sum : out integer range 2 to 12;
Roll, Win, Lose : out bit); end component;
signal roll1 : bit;
signal sum1: integer range 2 to 12;
begin
Dice:Dicegame
port map(Rb,Reset,Clk,sum1,roll1,Win,Lose);
Counter port map(Clk,roll1,sum1);
end Play1;

20. Implementation of Dice gameRb
PLA
Reset
Win
D711
Lose D7
Roll
D2312 Sp Eq C+ D Q CK C B+ B A+ A
Clock
<PLA Realization of Dice Game Controller>

21. PLA Table for Dice Game ABC Rb Reset D7 D711 D2312 Eq A+ B+ C+ Win
Lose
Roll Sp 1
000 - 2 3
001 4 5 6 7
010 8 9
011 10 11
100 12 13
101 14 15 16 17
110 18
111

22. Maps Derived from the previous table
A+ = A’B’CRb’D’711D’2312+AC’+ARb+AD’7Eq’,
B+ = A’B’CRb’(D711+D2312)+Breset’+ACRb’(Eq+D7)
C+ = B’Rb+A’B’CD’711D2312+BCReset’+ACD7Eq’,
Win = BC’, Lose = BC, Roll = B’CRb
Sp = A’B’CRb’D’711D’2312

23. Data Flow Model for Dice Game
architecture Dice_Eq of DiceGame is
signal Sp, Eq, D7, D711, D2312 : bit : =‘0’;
signal DA, DB, DC, A, B, C, : bit : =‘0’;
signal Point : integer range 2 to 12 ;
begin
process(CLK)
if rising_edge(CLK) then
A<=DA; B<=DB; C<=DC;
if Sp=‘1’ then Point<=Sum; end if;
end if
end process ;

24. Data Flow Model for Dice Game
Win <=B and not C:
Lose <=B and C;
Roll <= not B and C and Rb;
Sp <= not A and not B and C and not Rb and not D711 and not D2312;
D7 <=‘1’ when Sum=7 else ‘0’;
D711 <=‘1’ when (Sum=11) or (Sum=7) else ‘0’;
D2312<=‘1’ when (Sum=2) or (Sum=3) or (Sum=12) else ‘0’;
Eq <=‘1’ when Point=Sum else ‘0’;
DA <= (not A and not B and C and not Rb and not D711 and not D2312) or (A and not C) or (A and Rb) or (A and not D7 and not Eq)
DB <=( (not A and not B and C and not Rb) and (D711 or D2312) ) or (B and not Reset) or ( (A and C and not Rb) and (Eq or D7) );
DC <= (not B and Rb) or (not A and not B and C and not D711 and D2312) or (B and C and not Reset) or (A and C and D7 and not Eq);
End Dice_Eq;

25. Alternative realizations for SM Charts using Microprogramming
<Control Network Using an Input MUX to Select the Next State>
PLA or ROM or PAL
TEST NSF NST OUTPUT
Register
Inputs ． ．
MUX1
MUX2
◁ The only input to PLA come from state register
◁ Test controls MUX1 with inputs
◁ NSF or NST decided by input’s BOOLEAN (NST: Next State True)
◁ Must have only Moore outputs (Outputs depend on only current state)

26. Linked State Machine A sequential machine becomes large and complex,
Desirable to divide the machine into several smaller machines linked together.
Each of the smaller machines is easier to design and implement.
Machine B
(called machine)
Machine A
(calling machine)
SOME
STATES
IDLE ZA
SA / ZA 1
OTHER
STATES ZB 1
SB/ ZB
OTHER
STATES