Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ Semiconductor Device Modeling and Characterization EE5342, Lecture 26 Spring 2003 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/ L26 17April03

n-channel enhancement MOSFET in ohmic region 0< VT< VG e- channel ele + implant ion Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ e-e- e- e- e- + + + + + + + + + + + + n+ Depl Reg p-substrate Acceptors VB < 0 L26 17April03

Fully biased n- channel VT calc L26 17April03

Values for fms with silicon gate L26 17April03

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** |Q’d,max|/q (cm-2) xd,max (microns) L26 17April03

I-V relation for n-MOS ohmic ID non-physical ID,sat saturated VDS,sat L26 17April03

MOSFET equivalent circuit elements Fig 10.51* L26 17April03

MOS small-signal equivalent circuit Fig 10.52* L26 17April03

MOS channel- length modulation Fig 11.5* L26 17April03

Analysis of channel length modulation L26 17April03

Channel length mod- ulated drain char Fig 11.6* L26 17April03

Associating the output conductance ID ID,sat VDS,sat VDS L26 17April03

SPICE mosfet Model Instance CARM*, Ch. 4, p. 290 L = Ch. L. [m] W = Ch. W. [m] AD = Drain A [m2] AS = Source A[m2] NRD, NRS = D and S diff in squares M = device multiplier L26 17April03

SPICE mosfet model levels Level 1 is the Schichman-Hodges model Level 2 is a geometry-based, analytical model Level 3 is a semi-empirical, short-channel model Level 4 is the BSIM1 model Level 5 is the BSIM2 model, etc. L26 17April03

SPICE Parameters Level 1 - 3 (Static) L26 17April03

SPICE Parameters Level 1 - 3 (Static) * 0 = aluminum gate, 1 = silicon gate opposite substrate type, 2 = silicon gate same as substrate. L26 17April03

SPICE Parameters Level 1 - 3 (Q & N) L26 17April03

Level 1 Static Const. For Device Equations Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni) - q*NSS*TOX/eOx VTO = as given, or = Vfb + PHI + GAMMA*sqrt(PHI) KP = as given, or = UO*eOx/TOX CAPS are spice pars., technological constants are lower case L26 17April03

Level 1 Static Const. For Device Equations b = KP*[W/(L-2*LD)] = 2*K, K not spice GAMMA = as given, or = TOX*sqrt(2*eSi*q*NSUB)/eOx 2*phiP = PHI = as given, or = 2*Vt*ln(NSUB/ni) ISD = as given, or = JS*AD ISS = as given, or = JS*AS L26 17April03

Level 1 Static Device Equations vgs < VTH, ids = 0 VTH < vds + VTH < vgs, id = KP/2*[W/(L-2*LD)]*[vgs-VTH-vds/2] *vds*(1 + LAMBDA*vds) VTH < vgs < vds + VTH, id = KP*[W/(L-2*LD)]*(vgs - VTH)^2 *(1 + LAMBDA*vds) L26 17April03

References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997 L26 17April03