Central Processing Unit CPU Chapter 4 Central Processing Unit CPU 10/11/2018 cis110 - CPU

Learning outcomes By the end of this Chapter you will be able to: explain the components of the CPU and their functions explain the instruction format and the instruction cycle illustrate How the CPU execute instructions explain the details of the execution of instructions Explain different ways of improving computer performance: Clock frequency, Cache memory, Pipelining, CISC and RISC 10/11/2018 cis110 - CPU

Additional Reading Essential Reading Further Reading Stalling (2003): Chapters 3.1 - 3.4, 4.2, 12.4, 13.4 Further Reading Burrell (2004): Chapters 5 and 8 Schneider and Gersting (2004): Chapters 5 Brookshear (2003): Chapter 2 10/11/2018 cis110 - CPU

Introduction (1) How ? Before: Now: To run a program: how information is stored in an abstract level. Now: How information is processed in the computer? To run a program: First it is turned into machine code which consists of 1s and 0s. The machine code is loaded into the main memory and then executed by the CPU. How ? 10/11/2018 cis110 - CPU

Central Processing Unit The central processing unit (CPU) is the “brain” of the computer. It: interprets instructions to the computer (control unit), performs the arithmetic and logical processing (ALU) 10/11/2018 cis110 - CPU

Central Processing Unit - CPU The machine-code program can be divided into 2 parts: instructions and data. Instructions ask the CPU to take a particular action (do a job). Data (numbers, characters, letters, sounds, colours, etc.) The CPU execute a machine-code program as follows: it fetches an instruction, execute it then goes to fetches the next instruction and execute it. It follows fetch-execute cycle until all instructions are executed. 10/11/2018 cis110 - CPU

Basic Instruction Cycle Fetch next instruction Execute instruction Halt Start 10/11/2018 cis110 - CPU

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Component of the CPU Registers Program counter Accumulator Arithmetic Logic unit. Control Unit. 10/11/2018 cis110 - CPU

Registers Memory Address Register (MAR) Memory Buffer Register (MBR) Stores the address of the cell the CPU is going to execute. Memory Buffer Register (MBR) Contains instruction or data just read from the memory. Or data that is about to be written in the memory. Instruction Register (IR) Holds the instruction just fetched from the main memory. 10/11/2018 cis110 - CPU

I tells CPU to execute the instruction Program Counter - PC In contains the address of the next instruction. i.e. I = 100 1101 I tells CPU to execute the instruction stored in the address 1101. PC = 1101 10/11/2018 cis110 - CPU

Arithmetic Logic Unit- ALU It performs all arithmetic operations and Boolean logical operations. 10/11/2018 cis110 - CPU

It tells CPU to execute the instruction Control Unit It is the portion that allows things to happen. It controls all operations. It tells CPU to execute the instruction stored in the address 1101. control unit PC = 1101 10/11/2018 cis110 - CPU

ALU, Registers and Control Unit Relationships Data are presented to the ALU in registers. Performs operations and put the result back in registers Registers ALU Control unit Control operations. 10/11/2018 cis110 - CPU

CPU and System Bus MAR Address bus Registers ALU MBR Data bus Control unit Control bus 10/11/2018 cis110 - CPU

Instruction Format Op-code Operands instruction Operand Op-code Op-code indicates what the kind of operation to be performed. Operands Specifies the things that is to be operated on It is an address of a cell where some data are stored. instruction Operand Op-code 10/11/2018 cis110 - CPU

Example of Instruction 4 bits 12 bits address Op-code 16-bit instruction format 0001 = load the Accumulator (AC) from a cell in main memory 0010 = store the content of AC in a cell in main memory 0101 = Add to the AC the content of a cell in the main memory For example: 0001 000100000000  load AC with the data stored in 000100000000. 10/11/2018 cis110 - CPU

1940 5941 2 941 0003 0002 300 301 302 940 941 1940 5941 2941 0003 0002 300 301 302 940 941 PC AC IR 300 1940 PC AC IR 1940 5941 2941 0003 0002 301 0005 300 302 940 941 PC AC IR 3+2=5 1940 5941 2941 0003 0002 301 300 302 940 941 PC AC IR 10/11/2018 cis110 - CPU

1940 5941 2941 0003 0002 301 300 302 940 941 PC AC IR 0005 3+2=5 1940 5941 2941 0003 0005 302 300 301 940 941 PC AC IR 1940 5941 2941 0003 0002 302 0005 300 301 940 941 PC AC IR 10/11/2018 cis110 - CPU

Example: 8-bit Processor Opcode Operand Description 0 0 1 d d d d d Load the accumulator with the data 000 ddddd 0 1 0 a a a a a Add to the accumulator the data at the address aaaaa 1 0 0 Write the content of the accumulator to the address aaaaa 1 1 0 Make the content of the cell aaaaa to be 11111111 1 1 1 Halt Address Instruction 00000 001 10000 00001 010 10000 00010 100 10000 00011 110 10001 00100 111 00000 10000 000 00001 10001 000 11111 10/11/2018 cis110 - CPU

Six-Stage Instruction cycle Fetch real operand From memory Decode I Store result In M.M DI FO WO EI FI Perform Operation And store Result in A register CO Calculate operand address 10/11/2018 cis110 - CPU

Reading From The Memory Address of the required cell is put in MAR 1 This address is put into the address bus As MAR Address Bus 2 Control unit indicates READ operation 3 Cell in MM is activated and its content is put in Data Bus 4 The content is stored in MBR as As MBR DATA BUS 5 10/11/2018 cis110 - CPU

Writing to Memory Address of required cell is put in MAR 1 This address is put into the ADDRESS BUS As MAR ADDRESS BUS 2 The data to be written is put into MBR 3 The data(set of E. Sig.) is put on DATA BUS As MBR DATA BUS 4 CONTROL BUS indicates write operation 5 The cell is activated and the datum is put into it 6 10/11/2018 cis110 - CPU

Enhancing Computer Performance Desirable to make computers run faster. How can this be achieved? In a computer all information processing is done by the CPU. The speed of the CPU is the number of micro-operations it can perform in a second. 10/11/2018 cis110 - CPU

CPU Speed CPU consists of a set of registers, an ALU and Control Unit. CPU micro-operations are controlled by the control unit. The control unit issues a sequence of control signals at a fixed frequency. The control unit is able to do that as it is connected to a clock. 10/11/2018 cis110 - CPU

Clock A clock is a micro-chip that regulates the timing and speed of all computer functions. It includes a crystal that vibrates at a certain frequency when electricity is applied to it. The clock transmits a regular sequence of alternating 1s and 0s. cycle 10/11/2018 cis110 - CPU

Clock speed Also called clock rate, the speed at which a microprocessor executes instructions. Every computer contains an internal clock that regulates the rate at which instructions are executed and synchronizes all the various computer components. The CPU requires a fixed number of clock cycles to execute each instruction. The faster the clock, the more instructions the CPU can execute per second. Clock speeds are expressed in Megahertz (MHz) or Gigahertz (GHz). 10/11/2018 cis110 - CPU

Control Unit - Clock Control unit can issue one or more control signals in one clock cycle. This will enable the CPU to do one micro-operation per cycle, or a number of micro-operations simultaneously. Recent processor have a clock with frequency 2 GHz (2*230 Hz) (2* 230 micro-operation/ sec) 10/11/2018 cis110 - CPU

Cache Memory Main memory is slower than CPU. There is another clock between MM and CPU to co-ordinate the events on the system bus. If the CPU is connected directly to the main memory it will be slowed down by the lower clock rate of the bus. To ovoid this, a cache memory which can operate at nearly the speed of the CPU is put in between. 10/11/2018 cis110 - CPU

Cache and Main Memory Word transfer Word transfer CPU Cache Main CPU repeatedly accesses a particular small part of the main memory. In a short time a copy of this portion of the main memory is kept in the cache. 10/11/2018 cis110 - CPU

Read and Write with Cache Read a word from the main memory? The CPU checks whether the word is in the cache. If yes, the word is delivered to the CPU. If not, a block of the main memory containing the desired word is read into the cache and then passed to the CPU. Write data to the main memory? The CPU writes the data to the cache. Then, the cache writes the data to the main memory. 10/11/2018 cis110 - CPU

Pipelining Introducing parallelism into the sequential machine-instruction program. A number of instructions can be executed in parallel. Programs can run faster. 10/11/2018 cis110 - CPU

How does the CPU runs a program? The CPU runs a program by repeatedly performing an instruction cycle. Simple case: CPU fetches an instruction from the main memory. Executes the instruction Called instruction cycle (fetch-execute-cycle) 10/11/2018 cis110 - CPU

Example: Fetch-Execute-Cycle A two-stage cycle. Suppose we have 3 instruction I1, I2, I3. Without pipelining this will take 6 time units. With pipelining it will take only 4 time units. Why? 10/11/2018 cis110 - CPU

1 2 3 4 5 6 Fetch I1 I2 I3 Execute 1 2 3 4 5 6 Fetch I1 I2 I3 Execute Without pipelining Using pipelining 1 2 3 4 5 6 Fetch I1 I2 I3 Execute 1 2 3 4 5 6 Fetch I1 I2 I3 Execute 10/11/2018 cis110 - CPU

Six-Stage Instruction Cycle – without pipelining 5 instructions A, B, C, D, E 1 2 3 4 5 6 7 …. 12 ….. S1 A B S2 S3 S4 S5 S6 24 25 ……. 30 E D 10/11/2018 cis110 - CPU

Six-Stage Instruction Cycle – with pipelining 5 instructions A, B, C, D, E time stages 1 2 3 4 5 6 7 8 9 10 S1 A B C D E S2 S3 S4 S5 S6 It takes 6 time unit to finish the instruction A, and the other 4 instruction require 1 more time unit each to finish there execution Therefore the time required is 6 + 4 = 10 10/11/2018 cis110 - CPU

n-Stage Instruction Cycle Suppose we have m instruction Without pipelining n*m With pipelining n+m-1 time units. Explanation of the formulas: The first instruction takes n time unit to be executed completely. The other (m-1) instruction will require one time unit for each one of them to be executed completely. Therefore the time requires to execute m instruction in n-stage cycle is n+m-1. 10/11/2018 cis110 - CPU

Disadvantage of pipelining Data hazards. Structural hazards: Control hazards 10/11/2018 cis110 - CPU

Data Hazards Data hazards occur when data is modified. For example an operand is modified and read soon after. Because instruction may not finished writing to the operand, the second instruction may use incorrect data. 10/11/2018 cis110 - CPU

Example 1st intr write 2nd instr write 1st intr write 2nd instr read 10/11/2018 cis110 - CPU

Structural hazards Conflict in hardware resources Occurs when a part of the processor’s hardware is needed by two or more instructions at the same time Memory location etc, .. 10/11/2018 cis110 - CPU

Control hazards occur when the processor is told to branch ie, if a certain condition is true, jump from one part of the instruction stream to another one - not necessarily the next one sequentially. In such a case, the processor cannot tell in advance whether it should process the next instruction This can result in the processor doing unwanted actions. 10/11/2018 cis110 - CPU

Exercise What are the difficulties of pipelining in a conditional branch? An unconditional branch is effectively just one instruction in a straight sequence of instructions so the pipeline can keep flowing. With conditional branch, the processor has to make a decision which path it has to take. This can cause a problem if this decision depends on the result of an instruction which has not yet finished its path through the pipeline. In this case the processor may proceed along the wrong path and have to back up i.e. empty the pipe and start again. 10/11/2018 cis110 - CPU

Strategies to reduce the number of times the pipeline breaks Instruction buffers to fetch both possible instructions Prediction logic To fetch the most likely next instruction Delayed branch instructions Delays branch instructions By executing subsequent non-branch instruction irrespective of the branch outcome 10/11/2018 cis110 - CPU

Aims of RISC Reduce the number of instructions To simplify control unit freed chip used to allocate large number CPU registers. Small instruction format  fast decoding Addressing is referred to internal registers, not to the main memory Hence, Operands is faster Compiler generates better machine code. However, RISC programs have more instructions 10/11/2018 cis110 - CPU

Aims of CISC Large number of complex instructions Decoding is slower, Instructions have different addressing mode. Hence, fetching operands are complicated However, instructions are more expressive than RISC. Programming at assembly level is simpler CISC programs have less instruction than RISC 10/11/2018 cis110 - CPU

RISC Vs CISC computers RISC CISC Less instructions Fixed length instruction More registers Register to register computation, only load and store access memory More transistors on memory registers More instructions per program Reduce the number of cycles per instruction More instructions Variable length instrutions Less registers Memory to memory operations More transistors to store complex instructions Less instructions per program More 10/11/2018 cis110 - CPU

Summary Components of CPU Instruction format (op-code + operand ) How the CPU execute instructions How to write a machine code program Enhance computer performance Cache memory Pipelining Problems with pipelining Risc Vs Cisc 10/11/2018 cis110 - CPU