ADC32RF45 with KCU105 Internal Clock Fs @ 1.536 GHz

Hardware Setup

ADC32RF45 Hardware Setup Ensure JP3 is set to “INT CLK”. Connect an input signal to J2. This example uses a 220 MHz signal. Ensure C409 and C410 are installed as seen below.

Ini file placement Ensure the ADC32RF45_8224.ini file is in the correct folder. Note: this ini will work for the ADC32RF42 as well.

KCU105 Setup The KCU105 development board uses Ethernet and dual USB-to-UART capabilities to interface with a host computer and set up the FPGA correctly. To program the FPGA firmware, the bit file must be loaded using the Xilinx Vivado design tool. The first step will be to establish communication with the KCU105 board.   Open a serial port connection with any sort of serial terminal software, e.g. TeraTerm, Hercules, etc. Initialize a serial port communication to Silicon Labs Dual CP210x USB to UART Bridge: Enhanced COM Port. Click on “Setup” then select “Serial Port”. Set the baud rate of this serial connection to 115200, and leave all other defaults as set. Open another serial port connection and connect to Silicon Labs Dual CP210x USB to UART Bridge: Standard COM Port. Ensure the baud rate of this serial connection is 9600, leaving all other defaults as set.

KCU105 setup (cont.) Power up the KCU105 board. There should be information scrolling on the Enhanced COM port. Program the FPGA, doing the following steps: Open Xilinx Vivado 2016.1 design tool Double click on “Open Hardware Manager”. Click on “Open Target”, and select “Open New Target” Click on “Next” twice. Select the Hardware Target, and click “Next” again. Click on “Finish”. Click on “Program device”. Select xcku040_0. Navigate to the provided bit file for the project. Select the proper bit file: “KC105_TI_DHCP.bit.” Click on “Program device”. A new window will open showing the status of the programming. Once this reaches100%, the FPGA is programmed. The board IP address will be available on the Standard COM port. Next, the VADJ8 voltage must be set to 1.8V. This is set in the Enhanced COM port terminal. Navigate to the Enhanced COM port window. Return to the main menu by entering “0” in the terminal. Select “Adjust FPGA Mezzanine Card (FMC) settings” by entering “4” “Set FMC VADJ to 1.8V” by entering “4” Return to the main menu by entering “0” To check this voltage, select “Get the Power Systems Voltages” by entering “2” Enter “7” to “Get VADJ1D8 voltage.” The voltage should appear above the menu. Return to main menu by entering “0”

ADC32RF45EVM GUI Launch the ADC32RFxx EVM GUI, and click on the “Quick Start” tab. Select the following fields (as seen on the next slide): 1st Nyquist,LMX2582 to ADC, 1536 MSPS, Bypass, 12bit. NOTE: Internal Clk Frequency dropdown box may be grayed out, but you can still make a selection for 1536MSPS. Click Program EVM

ADC32RF42EVM GUI

In LMK04828 Clock Outputs window, set the CLKout 0 and 1 DCLK Divider to 16 as shown below.

HSDC Pro After connecting to the KCU105, select ADC32RF45_8224 in the dropdown box. Set the ADC output Data Rate to 1.536G. Click ok on the dialog box that pops up. Click Capture

Lane rate and Ref clock settings

HSDC Pro Capture