Chapter 6a IC/Package Co-Design for Power Integrity Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu

Outline Overview of Chip Package Co-design IO planning and placement Design constraints Multi-stage solutions Power integrity in package 2

Wire-bond vs Flip-chip Wire bonding Cheap Implementation Difficult to design IO signals are at boundary High inductance (~1nH) More worry on core and IO power distribution during design and analysis

Wire-bond vs Flip-chip IO cells can be over entire of chip area Low inductance (~0.1nH) High pin count, high cost Less worry on power delivery 4

Silicon Package Board (Cadence) 5

Connection from die to board Die (IO cells -> RTL routing -> bumps) -> package (bumps -> escape routing -> package routing -> balls) -> board 6

VLSI-Centric Design (Problematic) IC and package tools very separated: IC Physical Design Package Physical Design I/O Locations IBIS Models Package Modeling/Simulation IC Modeling/Simulation (From P. Franzon) 7

Needs of Chip-Package Co-Design High system frequency 400 MHz buses becoming common On-chip exposure to package noise Simultaneous switching noise Package resonance High density packaging and high pin count Difficult to layout and escape-route Again, more SSN for on-die circuit Tight time to market Convergence of package and IO becomes a bottleneck if chip and package handled by separated flows 8

Keys Problems to Solve Chip and package co-extraction and co-simulation Difficult to obtain accuracy for sign-off More difficult to achieve efficiency with accuracy or fidelity for planning and design Challenging to handle mutual inductance and large number of ports Co-design focuses on important links between chip and package Chip side: IO buffer design, noise isolation circuitry, P/G network, IO pad macro-placement, RDL estimation, Package side: Package stack-up, P/G plane design, macro-placement of balls and pins, and estimation of escape routing key issues: IO planning and placement, power delivery system 9

Outline Overview of Chip Package Co-design IO planning and placement Design constraints Multi-stage solutions Power integrity in package 10

Design Constraints for IO Planning and Placement Power integrity Timing I/O standards Core and board floorplanning

Power Integrity Constraints Power domain constraint I/O cell voltage specification Cells from same domain prefer physically closer Minimize power plane cut lines in the package Provide proper power reference plane for traces Depend on physical locations of I/O cells Proper signal-power-ground (SPG) ratio Primary and secondary P/G driver cells Minimize voltage drop and Ldi/dt noise

Timing Constraints Substrate routes in package varies significantly Length spans from 1mm to 21mm Timing varies more than 70ps for SSTL_2 I/O cells with critical timing constraints shall take this into account Differential pairs and bus prefer to escape in parallel and in same layer

I/O Standard Related Constraints High-speed design  high-speed I/O I/O standard requirements Relative timing requirements on signals Likely to be connected to the same interface at other chips, so prefer to keep relative order to ease routing Closeness constraint Less process variation Bump assignment feasibility constraint

Floorplan Induced Region Constraints Top-down design flow PCB floorplan Bottom-up design Chip floorplan I/O cells have region preference Which side? What location?

Connection from die to board Die (IO cells -> RTL routing -> bumps) -> package (bumps -> escape routing -> package routing -> balls) -> board 16

Flow of IO planning and placement Global I/O and Core co-placement Bump array Placement I/O site definition Constraint driven detailed I/O placement

Global I/O and Core Co-placement Minimize both wire length and power domain slicing Power domain plans I/O cells location, and becomes region constraints for I/O cells for the following steps

Bump and Site Definition Regular bump pattern is preferred Escapability analysis Regular I/O site is preferred I/O proximity RDL planar routability analysis I/O sites more than I/O cells SPG ratio consideration Flexibility for later bump assignment I/O super site: a cluster of I/O sites

Assign I/O Cells to Super I/O Sites A set of region constraints (Ri, CiR) A rectangular restricted area Ri for I/O cells CiR E.g., floorplan, power domain definition, wire length minimization A set of clustering constraints (Li, CiL) The spread of I/O cells should be less than a bound E.g., I/O standard const., floorplan, timing A set of differential pair constraints Different pairs should be connected to bumps with similar characteristics E.g., timing Solve by ILP or LP followed by netflow-based legalization

Experiment Setting Real industrial designs Constraints not include the ones that are generated internally 21

Experiment Result Obtain 100% CSR (constraint satisfaction ratio) in short runtime 22

Power Plane Cuts Core Domain Plane Cut Island IO Domain 23

Power Domain Routing Domain Routing 24

Outline Chip Package Co-design Flow IO planning and placement Power integrity in package Overview and modeling Decap insertion Impedance based Noise-based 25

Power Integrity Time domain power and signal integrity Signal Noise Analysis coupled with power plane models Superposition of Power Noise on Signal Noise IBIS, SPICE and PEEC models are employed Frequency domain analysis of Power Planes Impedance Return Path Modelling for EMI and SSN analysis EMI Analysis Package Plane Resonance 26

PDS: Power Distribution System Detailed Network Modeling is needed for accurate analysis of Core and IO Power 27

Ideal Package Power Planes Early Package Design Exploration Planes have no holes or perforations Perfect Microstrip or Stripline Patterns Impedance is well conditioned 28

Non-ideal Package Power Planes Detailed Plane Modeling Planes are split for different voltage domains Planes could have any number of holes / perforations Microstrip or Stripline Patterns: imperfect 29

PDS Modelling Wire capacitance can be extraction using 2.5D model [He-et al, DAC’97] With extension to arbitrary routing angle Plane capacitance needs to consider impact of wires in between Inductance is must and can be formula based Bonding wires have well controlled shapes Susceptance (L-1) makes sparsification easier But sign-off often needs 3D field solver 30

PDS Design Assign power planes in package stackup Assign power domains: V18, V25, Vanalog,… Decide via stapling Improve power delivery Reduce current loop and eliminate noise Assign P/G balls 31

PDS Concerns DC Concerns AC Concerns On-Chip IR Drop Not a big concern in Flip-chip Designs In-Package IR Drop Important but still very small In-PCB IR Drop Can be ignored AC Concerns Low impedance Network across a broad frequency spectrum Reduce inductive effective to reduce SSN Control Chip/Package resonance 32

Power Plane Noise (AC vs DC) 33

PDS Design PDS Impedance PDS Bandwidth Decide on Decap Allocation Smaller Zo  larger current PDS Bandwidth Maintain Zo from 0 to fmax Decide on Decap Allocation High speed drivers draw current from nearby decoupling capacitors Decoupling capacitors reduce the size of the current loop 34 34

Chip-Package Plane Resonance Resonances are produced due to inductance and capacitance Z Capacitor becomes inductive beyond its self resonant frequency, f(SR) Capacitive Inductive frequency Resonant frequency is Need a set of capacitors to cover small, medium, and high frequency ranges 35

Decoupling capacitors optimization Needs for power integrity Reduce resonance. Reduce effective inductance and resistance. Different levels of decoupling capacitors Board, package, chip Different effective frequency range. Decoupling capacitors is not perfect capacitor ESL ESR Lower ESL and ESR, higher cost Designing of decoupling capacitors needs to determine Values Location Decoupling capacitor type

Impact of decoupling capacitors

Existing Solutions Manual trial-and-error approaches [Chen et al., ECTC ’96] [Yang et al., EPEP 2002] Automatic optimization [Kamo et al., EPEP 2000], [Hattori et al., EPEP 2002] Ignore ESL and ESR. [Zheng et al., CICC 2003] Use impedance as noise metric [Chen et al., ISPD 2006] Noise driven decap insertion

Limit of Impedance Metric Can not capture noise accurately Will Lead to large over-design

Incremental impedance computation When adding one decoupling capacitor Zd at port k the new impedance from port j to port i is When removing one decoupling capacitor Zd at port k

Time complexity With one or a few decoupling capacitors inserted O(np2): np is the number of ports Existing work: O(np3) Especially suitable for trial-and-error or iterative methods Only a few decoupling capacitors changed in each iteration Able to compute only impedance or I/O ports before updating rest ports

Noise Calculation FFT methods Worst case noise from all ports Frequency components of noise from port j to port i Worst case noise from all ports Superposition

Algorithm Simulated annealing with objective function pi: Penalty function for noise violation ci: cost of decoupling capacitor α, β: weights

Example 4 types of decoupling capacitors 3 I/O ports Each connected to 10 I/O cells 90 possible location for decoupling capacitors Total 93 ports Worst case noise bound: 0.35V Power planes Type 1 2 3 4 ESC(nF) 50 100 ESR(Ω) 0.06 0.03 ESL(pH) 40 Price

Experiment results: noise based Type 1 2 3 4 ESC(nF) 50 100 ESR(Ω) 0.06 0.03 ESL(pH) 40 Price port 1 2 3 before optimization 2.52V 2.49V 2.48V after optimization 0.344V 0.343V Cost=20

Comparison: Impedance Based Cost=72 3X larger than noise based Impedance bound is not met but noise bound has already been met. Overdesign port 1 2 3 bound Maximum Impedance 5.31Ω 5.59Ω 7.12Ω 0.7Ω worst-case noise 0.256V 0.302V 0.284V 0.35V

Runtime Comparison 1 Noise via incremental impedance + decap 2 Noise via admittance matrix inversion [Zhao et al, EPEP 2004] + decap 3 Impedance + decap [Zheng et al, CICC 2003] approach 1 2 3 ports 93 20 iterations 5881 5403 1920 runtime(s) 389.5 4156.1 2916 avg. runtime(s) 0.0662 0.7692 1.519 10x speedup compared to method based on admittance matrix inversion

Recap of Key Points High-speed IO signaling requires package-aware design and analysis (co-design) Package-aware chip IO planning improves convergence and turnaround time On-chip devices are increasingly exposed to package effects Power integrity is getting harder Efficient and accurate macro models are needed to enable chip-package co-design 48

Benefit of Chip-Package Co-Design (Design from client of Rio Design Automation) ~24% reduction Package Size 27mm x 27mm Substrate Layers: 3-2-3 Original Die Size: 7.2 x 7.4mm New Die Size: 6.3 x 6.5 mm #Voltage Domains: 7 Two different voltages: 3.3V, 1.8V Total IOs: 341 Frequency: 200Mhz Original Bump pitch: x:225, y:225 New Bump Pitch: X:201, 225, 275 Y: 216, 225 TSMC 0.18u process

References Jinjun Xiong, YC Wong, Egino Sarto, Lei He, "Constraint Driven I/O Planning and Placement for Chip-package Codesign," IEEE/ACM Asia and South Pacific Design Automation Conference , 2006.  Jun Chen, Lei He, "Noise-Driven In-Package Decoupling Capacitance Insertion," IEEE/ACM International Symposium on Physical Design , 2006. 50